3.3 kW CCM Boost PFC Design: A Step-by-Step Engineering Example with Loss Budget

3.3 kW CCM Boost PFC Design: A Step-by-Step Engineering Example with Loss Budget

This article walks through a complete, production-ready design of a 3.3 kW single-phase Power Factor Correction (PFC) stage using Continuous Conduction Mode (CCM) Boost topology. Unlike conceptual overviews or rule-of-thumb approaches, this is a rigorously calculated engineering example grounded in real-world constraints: universal AC input (176–264 V_rms), 400 V DC bus, 133 kHz switching frequency, and a target efficiency of ≥97%. Every parameter—from inductor core selection to MOSFET parallel count and capacitor ESR impact—is derived from first principles, validated against vendor datasheets, and cross-checked for thermal and EMI compliance. The goal is not just “how to build it,” but how to engineer it correctly the first time.

Why CCM Boost for 3.3 kW? Topology Selection Logic

Topology choice is never arbitrary—it’s a direct function of power level, efficiency targets, EMI requirements, and control complexity. For single-phase PFC, the industry follows well-established boundaries:

• Discontinuous Conduction Mode (DCM): Suitable only for low-power applications (<200 W). Zero-current turn-on eliminates MOSFET switching loss and avoids diode reverse-recovery issues—but inductor current ripple becomes prohibitively large above ~150 W, demanding oversized magnetics and poor utilization of silicon.
• Boundary Conduction Mode (BCM): Ideal for 200–400 W. Offers natural zero-current switching (ZCS), simplifies control, and enables compact ferrite cores. However, variable-frequency operation spreads energy across a wide spectrum, complicating EMI filter design.
• Interleaved BCM: Extends the BCM sweet spot to ~2 kW. Two or more phases operating 180° out-of-phase cancel low-order current harmonics, reducing input filter size and improving THD. Still limited by variable-frequency challenges above 2 kW.
• Continuous Conduction Mode (CCM) Boost: The standard for >1 kW. Fixed-frequency operation (here, 133 kHz) confines harmonic energy to predictable sidebands, easing conducted-EMI compliance. With modern SiC diodes and optimized gate drivers, CCM achieves >97% efficiency at 3.3 kW without resonant or soft-switching add-ons.

At 3.3 kW, CCM is the optimal balance of efficiency, predictability, maturity, and cost. Three-phase PFC offers higher efficiency and lower per-phase current but introduces significant complexity: three-channel current sensing, multi-phase PWM timing, and advanced DSP-based control algorithms—overkill for many industrial and telecom power supplies. Interleaved CCM is viable but adds gate-drive complexity and IC-level synchronization overhead. This design uses a single-phase CCM Boost at 133 kHz—a deliberately aggressive frequency that minimizes inductor volume while keeping the fundamental (133 kHz) and its key harmonics (266 kHz, 399 kHz) safely below the 150 kHz conducted-EMI limit, simplifying common-mode choke design.

Input Current & Duty Ratio: Sizing for Worst-Case Stress

PFC design must begin at the most thermally and electrically stressful condition: minimum AC input voltage. At 176 V_rms, the input current reaches its maximum RMS value to deliver 3300 W at 97% efficiency:

I_{in_maxRMS} = P_out / (η · V_{in_min}) = 3300 W / (0.97 × 176 V) = 19.33 A

This 19.33 A RMS is the baseline for all downstream component ratings: rectifier bridge, input EMI filter, boost inductor winding, and current-sense resistor. It also defines the peak instantaneous current, which drives MOSFET and diode peak current ratings.

The duty ratio in CCM Boost varies dynamically with the rectified sine wave. Its instantaneous expression is:

D(t) = 1 − (√2 · V_in · sin(ω_pt)) / V_pfc

At minimum line (176 V), the maximum duty occurs at the peak of the sine wave (sin = 1):

D_min = 1 − (√2 × 176 V) / 400 V = 1 − 248.9 / 400 = 0.378

Thus, the converter operates between D ≈ 0.15 (at 264 V peak) and D ≈ 0.378 (at 176 V peak). This 0.378 duty sets the minimum on-time for MOSFET drive design and influences inductor volt-second balance calculations.

Boost Inductor Design: Core, Turns, and Loss Breakdown

The boost inductor is arguably the most critical passive component in CCM PFC. Its design requires simultaneous optimization of inductance value, saturation margin, core loss, copper loss, and DC bias behavior.

Inductance Value and Ripple Ratio

Following Maniktala’s recommended practice for balanced design, we select a peak-to-peak inductor current ripple ratio γ = 0.4 (i.e., ΔI_L = 0.4 × I_{in_maxRMS}). This avoids excessive core size (low γ) or excessive EMI filtering burden (high γ). The minimum inductance is calculated as:

L_min = (√2 · V_{in_min} · D_min) / (γ · f_s · I_{in_maxRMS})
= (248.9 V × 0.378) / (0.4 × 133 kHz × 19.33 A) = 91.43 µH

We select L_pfc = 92 µH as the target design value.

Core Selection Using Area Product (AP) Method

Using Faraday’s law, the required N·A_e product (Λ) is derived from the volt-second integral across the switching cycle:

Λ = ∫V_{ac_min}(t)·D_minIN(t)dt / (f_s · B_{s_avg}) = 60.914 cm²

Assuming a conservative average flux swing of B_{s_avg} = 0.1 T (appropriate for FeSiAl powder cores at 133 kHz to avoid runaway core loss), and a winding current density of 10 A/mm², the required wire cross-section is:

S_lead = I_{in_maxRMS} / J = 19.33 A / 10 A/mm² = 1.933 mm² → selected wire: 1.9 mm OD magnet wire (S_wire = 2.835 mm², actual J = 6.8 A/mm²).

With a realistic window fill factor K_w = 0.4, the required area product is:

AP = Λ · S_wire / K_w = 60.914 cm² × 2.835 mm² / 0.4 = 4.318 cm⁴

We select two Amosense APH36P60 toroids in parallel. Each core has A_e = 0.678 cm² and A_w = 3.64 cm², giving a combined AP = 2 × 0.678 × 3.64 = 4.936 cm⁴ — comfortably exceeding the 4.318 cm⁴ requirement.

Turns Calculation and DC-Bias Validation

Turns are calculated directly from Λ and effective core area:

N = Λ / (2 · A_e) = 60.914 cm² / (2 × 0.678 cm²) = 44.9 → N = 45 turns

Final fill factor K_w = 0.351 confirms mechanical feasibility. Crucially, we validate inductance under DC bias. The peak inductor current is:

I_{L_peak} = I_{in_maxRMS} × √2 + ΔI_L/2 = 19.33 A × 1.414 + (0.4 × 19.33 A)/2 = 27.33 A + 3.87 A = 31.2 A

Magnetizing force H_e = N × I_{L_peak} × √2 / l_e = 45 × 31.2 A × 1.414 / 8.98 cm = 221 Oe (well within the 100 Oe spec where µ remains stable). At 172 Oe (calculated for RMS current), µ drops to 40% of nominal, reducing inductance from 230.5 µH (zero bias) to 92.2 µH — matching our design target and confirming no saturation risk (B_max = 0.413 T << 1.5 T).

Choke Loss Budget

Core loss is modeled using Amosense’s PL formula for FeSiAl:

PL = 3.89 × (B/0.1T)^2.57 × (f/kHz)^1.11 kW/m³ → P_fe = 10.74 W

Copper loss: R_dc = ρ_cu × N × L_perturn / S_wire = 0.016 Ω → P_cu = I_{in_maxRMS}² × R_dc = 5.93 W

Total choke loss = 16.67 W

Power Semiconductor Selection and Loss Analysis

Component selection is driven by voltage stress, current rating, thermal resistance, and loss composition—not just headline specs.

MOSFETs: Parallel 600 V Devices for Low R_DS(on)

Voltage stress equals the PFC output voltage (400 V), plus margin for ringing and overshoot. A 20% derating yields 480 V, so 600 V-rated devices are mandatory. We select two Infineon SPW20N60C3 (TO-247) in parallel:

• V_DS = 600 V, I_D = 20 A (T_c = 100 °C)
• R_DS(on) = 0.22 Ω @ T_j = 60 °C (critical for conduction loss)
• Switch RMS current = 13.28 A → per-device RMS = 6.64 A

Conduction loss: P_c = I_RMS² × R_DS(on) = (13.28 A)² × 0.22 Ω = 19.39 W
Switching loss (tr = 5 ns, tf = 4.5 ns): P_s = 0.5 × V_pfc × I_pk × (tr + tf) × f_s = 3.12 W
Total MOSFET loss = 22.51 W

Upgrading to SPW35N60C3 (R_DS(on) = 0.119 Ω) reduces conduction loss by ~8 W but increases cost and layout complexity—illustrating the classic efficiency/cost trade.

Boost Diodes: SiC Eliminates Reverse Recovery

Diode voltage stress = V_pfc = 400 V → 600 V rating required. Traditional silicon fast-recovery diodes suffer severe reverse-recovery loss and EMI at 133 kHz. Two ST STPSC806 SiC Schottky diodes in parallel solve both:

• V_RRM = 600 V, I_{F_RMS} = 18 A, V_F = 1.4 V @ 15 A
• No reverse recovery charge (Q_rr ≈ 0) → zero switching loss, clean turn-off waveform
• Diode RMS current = 14.05 A → per-diode = 7.03 A ✓

Diode loss = V_F × I_{F_AVG} + I_{F_RMS}² × R_d = 1.4 V × 8.51 A + (14.05 A)² × 0.025 Ω = 21.36 W

Input Rectifier Bridge: The Hidden Efficiency Limiter

The full-wave bridge conducts the full 19.33 A RMS input current. Standard 600 V bridges have V_F ≈ 0.95 V:

P_bridge = 2 × V_F × I_{in_maxRMS} = 2 × 0.95 V × 19.33 A = 33.07 W

This single component accounts for ~32% of total PFC losses—the largest contributor. That’s why bridgeless PFC topologies (which eliminate two diode drops) can yield a hard-won +0.5% efficiency gain, making them attractive for premium 3.3 kW designs despite doubled device count and control complexity.

Output Capacitor Selection: Ripple, ESR, and Lifetime

The 400 V DC bus capacitor smooths the twice-line-frequency (100/120 Hz) ripple from the boost diode current. Target ripple is ≤6% peak-to-peak of V_pfc (24 V). Required capacitance:

C_pfc = I_{diode_RMS} × √2 / (2π × 2f_p × V_pfc × 0.06) = 1317 µF

We select three Rubycon USC 470 µF / 450 V electrolytics in parallel (C_total = 1410 µF). Key validation points:

• Ripple current rating: 2.35 A @ 120 Hz per cap → total RMS current = 6.01 A → 2.0 A per cap ✓
• ESR ≈ 0.282 Ω (from tanδ = 0.25) → ripple voltage RMS = 6.01 A × 0.282 Ω = 7.0 V → peak-to-peak = 19.8 V = 4.95% ✓
• Capacitor loss: P_cap = I_RMS² × ESR = (6.01 A)² × 0.282 Ω = 10.2 W

Electrolytic ESR is a dominant lifetime factor—higher ESR means higher internal temperature rise, accelerating wear-out. This 10.2 W loss directly impacts long-term reliability.

Complete Loss Budget and Efficiency Verification

Summing all major losses at the worst-case 176 V condition gives the true system efficiency:

Efficiency at 176 V = P_out / (P_out + P_loss) = 3300 W / (3300 W + 103.8 W) = 96.9%

At nominal 220 V input, losses decrease due to lower input current and reduced duty ratio, yielding 97.6% efficiency. A bridgeless variant would reduce bridge loss from 33.07 W to ~16.5 W, pushing efficiency toward 98.0%.

Control Loop & Analog Peripheral Design Highlights

While digital controllers dominate new designs, analog implementation remains vital for cost-sensitive or legacy platforms. Key parameters from the Mathcad sheet:

• Voltage Feedback: Divider sets V_pfc = 405.7 V (slightly above 400 V to ensure regulation under load). Compensation network (C_p = 330 nF, R_z = 33 kΩ, C_z = 3.3 µF) yields crossover at ~13.8 Hz and phase margin of 47.4°—stable and robust.
• Brown-Out Protection: Hysteresis set by R_boU/R_boL triggers turn-on at ~175 V and turn-off at ~151.5 V, with 1 µF timing capacitor providing ~5-cycle delay (τ ≈ 5 line cycles) to reject transients.
• Current Sensing: R_sense = 10 mΩ keeps dissipation ≤3 W. Overcurrent threshold set by R_cs = 1.91 kΩ → I_ocp = 34.4 A, safely above inductor peak (32.8 A). RC filter (R_M = 100 kΩ, C_M = 330 pF) provides ~5 switching-cycle response time.

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