1500W PFC + Phase-Shifted Full-Bridge Power Supply: Board-Level Teardown and Analysis

This article presents a comprehensive board-level teardown and technical analysis of a commercial 1500W industrial-grade AC–DC power supply featuring an active continuous-conduction-mode (CCM) boost PFC front-end followed by a phase-shifted full-bridge (PSFB) DC–DC stage. Designed for high-efficiency, high-reliability applications—including telecom rectifiers, server PSUs, and industrial motor drives—the unit delivers regulated 48 VDC at up to 31.25 A with peak efficiency exceeding 95.2% at full load.

Board Architecture Overview

The main PCB is a double-sided, 6-layer FR-4 board with dedicated internal planes for power distribution (V_bus, ground, and control return). It is partitioned into three physically isolated zones:

PFC Stage Zone: Left third—contains boost inductor, MOSFETs, input EMI filter, and bulk capacitor bank (2 × 470 µF/450 V electrolytics in parallel).
PSFB Stage Zone: Central third—houses the transformer, four primary-side MOSFETs (SiC), synchronous rectifier FETs, and output LC filter.
Control & Monitoring Zone: Right third—hosts dual microcontrollers (one for PFC, one for PSFB), isolated gate drivers, current/voltage sensing circuitry, and digital communication interfaces (PMBus v1.3).

Thermal management employs forced-air cooling via a 60 mm axial fan (controlled via PWM based on heatsink temperature), with aluminum heatsinks thermally coupled to both PFC and PSFB MOSFETs using 1.5 W/m·K thermal interface material.

PFC Front-End: Design and Control Circuit Analysis

The PFC stage operates in average-current-mode CCM with interleaved control (single-phase, non-interleaved here). Input specifications are 85–264 VAC, 47–63 Hz. Key design parameters:

Boost inductor: 42 µH, gapped ferrite core (EFD55), rated for 25 A RMS, 40 A peak.
Boost switch: STW62N65M5 (650 V, 62 A, R_DS(on) = 42 mΩ @ T_j = 100°C).
Boost diode: STTH1212D (1200 V, 12 A, soft recovery).
Output bus voltage: 400 VDC ±2%, regulated via voltage-mode feedback loop with Type-II compensation.

Control is implemented using an Infineon ICE2PCS01 dedicated PFC controller. The IC integrates zero-current detection (ZCD), overvoltage protection (OVP), and cycle-by-cycle current limiting. The voltage feedback network uses a precision 0.1% resistor divider (R1 = 1.0 MΩ, R2 = 10.0 kΩ) feeding into the VSENSE pin. Current sensing employs a 2 mΩ, ±0.5% shunt resistor placed on the low-side source path of the boost MOSFET, amplified 25× via a matched-opamp circuit (INA240A2).

The PFC controller’s internal error amplifier sets the current reference ramp; the resulting duty cycle is modulated across line cycles to maintain sinusoidal input current with THD < 5% at full load.

Phase-Shifted Full-Bridge Main Stage: Topology and Parameters

The PSFB stage converts the 400 VDC bus to regulated 48 VDC. Its key advantages over conventional full-bridge include ZVS operation across wide load ranges, reduced switching losses, and inherent transformer reset capability.

Key component selections:

Primary switches: Four CREE C3M0065100K (1000 V, 65 mΩ SiC MOSFETs) mounted on a common heatsink.
Transformer: Custom planar magnetics design, EE85 core, 12:1 turns ratio (primary:secondary), 120 µH magnetizing inductance, leakage inductance ≈ 4.8 µH (intentionally leveraged for ZVS).
Secondary rectification: Four paralleled SiC Schottky diodes (C4D20120D) plus active synchronous rectification using six 40 V, 100 A NexFETs (CSD18540Q5B) driven by UCC27531 gate drivers.
Output filter: 2 × 1000 µF/63 V POSCAPs in parallel + 2.2 µH shielded toroid (custom-wound).

ZVS is achieved by introducing controlled phase shift between diagonally opposing switch pairs (Q1/Q4 vs Q2/Q3). The dead time between complementary drive signals is dynamically adjusted by the PSFB controller to ensure sufficient resonant energy for turn-on. At light loads (<10%), auxiliary ZVS assist circuitry (a small resonant capacitor across the primary winding) engages to maintain soft switching.

Control Boards and Digital Implementation

Two independent control boards communicate via SPI and share a common isolated 3.3 V rail. Each board features its own isolated DC–DC converter (RECOM RxxPxx series) and galvanically isolated signal paths (Si86xx digital isolators).

The PSFB controller is a TI C2000™ TMS320F280049C microcontroller running real-time firmware at 100 MHz. Critical timing-critical functions—including phase-shift calculation, adaptive dead-time adjustment, and current-mode slope compensation—are executed in hardware-accelerated peripherals (ePWM modules with trip-zone logic and CMPSS comparators).

The PFC controller board uses a smaller MSP430FR5994 MCU for supervisory tasks: fan speed control, fault logging, PMBus command parsing, and coordination with the PSFB controller during startup sequencing (e.g., ensuring bus voltage reaches ≥380 V before enabling PSFB).

Component Selection and Layout Observations

Several layout decisions reflect careful attention to EMI mitigation and thermal performance:

High-frequency current loops (e.g., PFC switch node, PSFB bridge legs) are minimized using tightly coupled copper pours and symmetric routing. The PFC boost diode’s cathode trace runs directly beneath the inductor’s top winding layer to reduce parasitic inductance.
Grounding strategy: A split ground plane separates analog-sensing grounds (low-noise AGND) from high-current power grounds (PGND), joined only at a single star point near the bulk capacitors.
Capacitor placement: Bulk electrolytics are located within 10 mm of their respective switching nodes; ceramic decoupling caps (100 nF X7R, 10 µF X5R) are placed adjacent to each gate driver IC.
Isolation barriers: Creepage/clearance distances exceed IEC 62368-1 requirements (≥8 mm between primary and secondary circuits); reinforced insulation is verified using 3 kV AC hipot testing.

Comparative Analysis: PSFB vs. LLC Resonant Converter

For 1500W, 48 V output, the PSFB was selected over LLC due to superior load-transient response and tighter regulation under dynamic loading—critical for datacenter applications. However, PSFB demands more complex control and higher gate-drive power. The following table summarizes tradeoffs:

Parameter	Phase-Shifted FB	LLC Resonant
Peak Efficiency	95.2% @ 1500 W	95.8% @ 1200 W
Regulation Bandwidth	≈ 25 kHz	≈ 8 kHz
ZVS Load Range	10–100% load	30–100% load
EMI Profile	Sharper spectral peaks, requires tuned input filter	Lower harmonic content, smoother spectrum

Firmware Snippet: Adaptive Dead-Time Calculation

The PSFB controller dynamically adjusts dead time (DT) based on bus voltage and load current to maintain robust ZVS while minimizing conduction loss. Below is simplified pseudocode reflecting the actual implementation:

// Inputs: Vbus (measured), Iout (estimated), Tj (heatsink temp)
// Outputs: DT_us (dead time in microseconds)

float calc_dead_time(float Vbus, float Iout, float Tj) {
  float base_dt = 280.0f; // nominal DT at 400V, 25°C
  float dt_adj_v = (Vbus > 400.0f) ? (Vbus - 400.0f) * 0.35f : 0.0f;
  float dt_adj_i = (Iout > 15.0f) ? (Iout - 15.0f) * 1.2f : 0.0f;
  float dt_adj_t = (Tj > 70.0f) ? (Tj - 70.0f) * 0.8f : 0.0f;

  float final_dt = base_dt + dt_adj_v + dt_adj_i + dt_adj_t;
  return clamp(final_dt, 220.0f, 450.0f); // enforce safety bounds
}

Frequently Asked Questions

Q1: Why use SiC MOSFETs in both PFC and PSFB stages?
SiC devices enable higher switching frequencies (reducing passive size), lower conduction losses at high temperatures, and improved ZVS margin—especially critical in the PSFB primary side where hard-switching would otherwise dominate losses at light loads.

Q2: How is transformer saturation avoided during startup or overload?
The controller implements a “soft-start” routine that ramps phase shift gradually over 20 ms. Additionally, the current-mode control loop limits peak primary current to 32 A via cycle-by-cycle blanking and fast overcurrent shutdown (response < 200 ns) using hardware comparators tied to the primary current sense transformer.

Q3: What contributes most to achieving >95% efficiency at full load?
Three interdependent factors: (1) SiC-based primary switching with <1.2 W conduction loss per device, (2) synchronous rectification reducing secondary conduction loss by ~65% versus diodes, and (3) optimized magnetics with <0.8% core loss at 100 kHz operating frequency.