H-Bridge Gate Drive Circuit Design: NMOS, PMOS and IR2110 Bootstrap

H-Bridge Gate Drive Circuit Design: NMOS, PMOS and IR2110 Bootstrap

In modern power electronics—especially in motor drives, UPS systems, and solar inverters—the H-bridge is the foundational topology for bidirectional power conversion. Its ability to reverse current flow and synthesize AC waveforms from DC makes it indispensable. Yet, its simplicity in schematic form belies the complexity of robust gate drive implementation. Poorly designed gate drive circuits lead to shoot-through, excessive switching losses, MOSFET destruction, and system instability. This article details critical design considerations for H-bridge gate drivers, comparing N-channel vs P-channel topologies, explaining high-side bootstrap operation with the IR2110, integrating opto-isolated drivers like the TLP250, selecting optimal gate resistors, enforcing dead-time, and diagnosing common failure modes.

N-Channel vs P-Channel MOSFET H-Bridges

Early H-bridge designs often used complementary MOSFETs: P-channel devices on the high-side and N-channel on the low-side. While this avoids high-side level-shifting challenges, P-channel MOSFETs suffer from significantly higher R_DS(on), larger die area, slower switching speeds, and limited voltage/current ratings. In contrast, N-channel MOSFETs offer superior conduction and switching performance across all voltage classes (60 V to 1.7 kV). Consequently, modern high-efficiency H-bridges universally adopt all-N-channel topologies, requiring active high-side gate drive solutions.

The trade-off is gate drive complexity: the high-side N-MOSFET’s source terminal floats at the output node voltage (0 V to V_bus). To turn it on, its gate must be driven ~10–15 V above the source—not above ground. This necessitates a floating, self-referenced supply—a challenge elegantly solved by bootstrap techniques.

Bootstrap Operation with the IR2110

The IR2110 (Infineon) is a high-voltage, high-speed dual-channel driver combining a grounded low-side driver and a floating high-side driver powered via bootstrap. Its architecture includes an internal level shifter, undervoltage lockout (UVLO), and logic-input compatibility (CMOS/TTL).

During the low-side conduction phase, the high-side source (i.e., the bridge output node) is near ground. A bootstrap diode (e.g., 1N4148 or fast recovery Schottky) charges the bootstrap capacitor (typically 0.1–1 µF ceramic + 10 µF electrolytic) from the V_CC rail (12–15 V). When the low-side switch turns off and the high-side is commanded on, the capacitor provides the gate-source voltage (V_GS) referenced to the now-rising source node. The capacitor discharges only through gate leakage and driver quiescent current—so duty cycle limitations apply: continuous 100% high-side conduction is impossible without auxiliary supply.

Key design rules:

• Bootstrap diode must withstand V_bus + V_CC reverse voltage and support fast recovery (< 50 ns t_rr).
• Bootstrap capacitor ESR must be low; use X7R ceramic in parallel with low-ESR electrolytic.
• Minimum off-time between high-side on-pulses must exceed the time needed to recharge the capacitor—typically > 1–2 µs per volt of V_bus.

Opto-Isolation: Integrating the TLP250

For galvanic isolation—critical in high-voltage inverters (>400 VDC bus) or systems with noisy grounds—the TLP250 optocoupler provides 2.5 kV_RMS isolation and 0.6 A peak gate drive. Unlike the IR2110, it lacks built-in level shifting and UVLO, so external circuitry is required.

A typical isolated high-side driver uses the TLP250 feeding a discrete buffer stage (e.g., complementary BJT pair or dedicated gate driver IC like TC4420) to deliver sufficient peak current. The input side receives PWM from a microcontroller; the output side references its own isolated supply (e.g., DC-DC converter module). Isolation prevents ground loops, protects controllers from fault transients, and enables multi-level topologies.

Gate Resistor Selection: Balancing Speed and Stability

The gate resistor (R_g) critically shapes switching behavior:

• Too small: Excessive dV/dt and di/dt → EMI, parasitic oscillation, Miller-induced false turn-on, and high peak gate current stressing the driver.
• Too large: Slow transitions → increased switching losses (E_sw ∝ t_rise + t_fall), thermal stress, and reduced maximum PWM frequency.

Design starts with the MOSFET’s total gate charge Q_g (from datasheet) and desired switching time t_sw. For a driver with output impedance R_drv, approximate R_g ≈ t_sw / (2.2 × C_iss), but empirical validation is essential. Typical values range from 2.2 Ω (high-power, fast-switching) to 47 Ω (low-noise, low-frequency applications). A gate resistor network—e.g., 10 Ω series + 2.2 Ω pulldown with anti-parallel diode—enables asymmetric turn-on/turn-off for optimized loss distribution.

Shoot-Through Prevention and Dead-Time Implementation

Shoot-through occurs when both high-side and low-side switches in the same leg conduct simultaneously, creating a low-impedance path across the DC bus. Even sub-microsecond overlap can cause catastrophic current spikes, device failure, and bus collapse.

Prevention requires two layers:

1. Hardware interlock: Using cross-coupled logic (e.g., NAND gates) to ensure complementary signals cannot be high simultaneously.
2. Controlled dead-time: Introducing a fixed, non-overlapping delay (typically 100–1000 ns) between turn-off of one switch and turn-on of the other.

Microcontroller-based PWM peripherals (e.g., STM32 TIMx, TI C2000 ePWM) provide configurable dead-time units that insert precise delays automatically. Below is pseudo-code illustrating dead-time insertion in firmware:

// Pseudo-code: Dead-time insertion for complementary PWM
// Assumes timer channel A = high-side, channel B = low-side
TIMx_CCR1 = duty_cycle;        // High-side compare value
TIMx_CCR2 = duty_cycle;        // Low-side compare value
TIMx_BDTR.DT = 300;            // 300 ns dead-time (scaled per timer clock)
TIMx_BDTR.AOE = ENABLE;        // Auto-output enable
TIMx_BDTR.MOE = ENABLE;        // Main output enable

Common Failure Modes and Mitigations

Despite careful design, field failures persist. Root causes include:

• Bootstrap capacitor undercharge: Caused by insufficient low-side on-time or high switching frequency. Mitigation: Monitor bootstrap voltage with comparator; reduce max duty cycle or add charge pump.
• Miller turn-on: Rapid dV/dt across high-side drain-source couples through C_rss, raising gate voltage unintentionally. Mitigation: Use negative turn-off bias (–5 V), gate resistors with local pull-down, or active Miller clamp circuits.
• Ground bounce & layout-induced noise: Shared power/ground paths induce voltage offsets, corrupting logic thresholds. Mitigation: Star grounding, separate power/ground planes for logic and power sections, short and wide gate loops, and local decoupling (100 nF X7R + 10 µF tantalum) at each driver supply pin.
• Overvoltage transients: Inductive kick during turn-off exceeds V_DS(max). Mitigation: RC snubbers, TVS diodes across MOSFETs, and proper PCB trace inductance minimization.

Topology Comparison: N-Channel vs P-Channel H-Bridge

Parameter	All-N-Channel (Bootstrap)	Complementary (P+N)
Typical RDS(on) @ 100 V	2–5 mΩ (N-MOS)	25–60 mΩ (P-MOS)
Max Practical Bus Voltage	600 V (with care)	≤ 60 V (limited P-MOS availability)
Gate Drive Complexity	Medium (bootstrap + timing constraints)	Low (no level shift needed)
Thermal Performance	Superior (lower conduction loss)	Inferior (higher RDS(on), uneven heating)
Cost per kW	Lower (smaller heatsinks, fewer devices)	Higher (larger P-MOS dies, derating)

Frequently Asked Questions

Q: Can I use the IR2110 for 100% duty cycle high-side operation?
A: No. The bootstrap capacitor requires periodic low-side conduction to recharge. For 100% duty cycle, use a dedicated isolated DC-DC supply or a charge-pump driver (e.g., IRS21844 with integrated pump).

Q: Why do some designs place a 10–100 Ω resistor between gate and source on the high-side MOSFET?
A: This “gate pull-down” ensures the MOSFET stays firmly off during boot-up, startup transients, or driver fault conditions—preventing unintended turn-on due to noise or floating gate.

Q: Is it safe to omit gate resistors if my MOSFET has low Q_g?
A: Never omit them. Even low-Q_g devices exhibit parasitic inductance and capacitance. Uncontrolled ringing can exceed V_GS(max), destroy the gate oxide, or trigger shoot-through via coupled noise.