IGBT and MOSFET Loss Calculation and Heatsink Design for Inverters

Designing reliable, high-efficiency inverters demands rigorous power semiconductor loss analysis and thermally robust mechanical integration. Whether for industrial motor drives, renewable energy systems, or EV traction inverters, accurate estimation of conduction and switching losses—and their thermal consequences—is foundational to safe, long-life operation. This article details a systematic methodology for calculating IGBT and MOSFET losses in three-phase voltage-source inverters (VSIs), estimating junction temperature (T_j), selecting heatsinks with appropriate thermal resistance (R_th,hs), and validating forced-air cooling performance. Practical examples anchor theory to real-world constraints.

Loss Mechanisms in Power Switches

Power device losses fall into two categories: conduction loss (P_cond) and switching loss (P_sw). For IGBTs, conduction loss is dominated by the forward voltage drop (V_CE(sat)) across the collector–emitter path under on-state conditions; for MOSFETs, it stems from the on-resistance (R_DS(on)) and current squared (I_D²R_DS(on)). Switching loss arises during turn-on and turn-off transitions—when both voltage and current are simultaneously nonzero—and scales with switching frequency (f_sw), bus voltage (V_DC), load current (I_O), and device-specific energy per switching event (E_on, E_off).

Conduction Loss Calculation

In a three-phase inverter operating with space-vector PWM, each switch conducts for approximately one-third of the fundamental period—but only half the time at full bus voltage due to complementary switching. A widely adopted approximation for average conduction loss per device is:

P_cond ≈ (1/3) × I_rms² × R_DS(on)   [MOSFET]  
P_cond ≈ (1/3) × I_rms × V_CE(sat)   [IGBT]

where I_rms is the RMS phase current. For a 100 A RMS motor drive with an IGBT rated at V_CE(sat) = 2.1 V at 100 A, P_cond ≈ (1/3) × 100 × 2.1 = 70 W per switch. Six devices yield ~420 W total conduction loss.

Switching Loss Estimation

Switching loss per device is calculated as:

P_sw = f_sw × (E_on + E_off)

Values for E_on and E_off are extracted from datasheet graphs (typically vs. I_C and V_CE), often requiring interpolation. At 8 kHz switching frequency and 600 V DC link, a typical 1200 V/100 A IGBT may exhibit E_on = 3.2 mJ and E_off = 4.5 mJ. Thus:

P_sw = 8000 × (3.2 + 4.5) × 10⁻³ = 61.6 W per device

Total switching loss for six switches: ~370 W. Note that E_on and E_off increase with junction temperature—a critical feedback loop in thermal design.

Junction Temperature Estimation

The junction-to-ambient thermal path comprises three resistances in series: junction-to-case (R_th,jc), case-to-heatsink (R_th,cs), and heatsink-to-ambient (R_th,hs-a). The steady-state junction temperature is:

T_j = T_a + P_total × (R_th,jc + R_th,cs + R_th,hs-a)

Where P_total = P_cond + P_sw per device. For our example: P_total = 70 + 61.6 = 131.6 W. Assuming R_th,jc = 0.15 K/W, R_th,cs = 0.05 K/W (with 1 W/m·K thermal interface material, 0.1 mm thickness, 10 cm² contact area), and ambient T_a = 40 °C, solving for required R_th,hs-a given max T_j = 125 °C:

R_th,hs-a ≤ (125 − 40) / 131.6 − (0.15 + 0.05) ≈ 0.43 K/W

This defines the maximum allowable heatsink thermal resistance.

Heatsink Thermal Resistance Selection

Heatsink resistance depends on geometry, material (aluminum extrusion vs. copper baseplate), fin density, airflow velocity, and orientation. Forced convection dramatically improves performance over natural convection. Empirical correlations (e.g., from manufacturer data sheets or standards like IEC 61800-5-1) relate R_th,hs-a to volumetric airflow (CFM) and surface area. A practical rule-of-thumb: doubling airflow reduces R_th,hs-a by ~30%.

Forced Air Cooling Considerations

Effective forced-air cooling requires attention to pressure drop, fan selection, ducting, and airflow uniformity. High-velocity air increases heat transfer coefficient but also fan power consumption and acoustic noise. Optimal mass flow rate balances thermal performance against system-level efficiency. Computational fluid dynamics (CFD) simulation is recommended for >10 kW inverters, but simplified models suffice for early-stage sizing:

Fan static pressure must exceed total system pressure drop (heatsink fins + ducting + filters).
Target face velocity: 2–4 m/s across heatsink frontal area.
Fin spacing: 8–12 mm for 2–5 m/s airflow—narrower spacing increases surface area but raises pressure drop nonlinearly.

Comparative Device Analysis: IGBT vs. Si-MOSFET

The following table compares representative 1200 V, 100 A-rated devices under identical 8 kHz, 600 V, 100 A RMS inverter conditions. All values assume T_j = 100 °C and include gate driver losses (negligible for IGBTs, ~2 W per MOSFET).

Parameter	IGBT Module (e.g., Infineon FF100R12ME4)	Si-MOSFET Module (e.g., STW90N120)
Conduction Loss (per switch)	70 W	42 W
Switching Loss (per switch)	61.6 W	112 W
Total Loss (per switch)	131.6 W	154 W
R_th,jc (K/W)	0.15	0.22
Required R_th,hs-a (K/W) @ T_j ≤ 125°C	0.43	0.39

Note the trade-off: MOSFETs offer lower conduction loss at low currents but suffer disproportionately higher switching loss at 8 kHz—making them less suitable for medium-frequency industrial inverters. However, above 20 kHz (e.g., in servo drives), MOSFETs often win overall efficiency. Wide-bandgap devices (SiC MOSFETs) shift this balance further—offering both low R_DS(on) and ultra-low E_sw.

Practical Thermal Design Example: 150 kW Traction Inverter

A liquid-cooled 150 kW, 650 Vdc, 300 A RMS traction inverter uses six 1200 V/400 A IGBT modules (e.g., Semikron SKM200GB12T4). Each module dissipates:

P_cond = (1/3) × 300 × 1.85 = 185 W
P_sw = 10,000 × (4.8 + 6.1) × 10⁻³ = 109 W
P_total = 294 W

With R_th,jc = 0.08 K/W, R_th,cs = 0.02 K/W, and coolant inlet at 65 °C, the target R_th,c-j (coolant-to-junction) must satisfy:

R_th,c-j ≤ (150 − 65) / 294 − (0.08 + 0.02) ≈ 0.185 K/W

This drives selection of a cold plate with microchannel flow, optimized for 8 L/min flow rate and ΔT < 5 K. Thermal interface material (TIM) must be applied uniformly (<0.1 mm thickness) to avoid voids—validated via IR thermography during prototype testing.

Implementation Tips and Pitfalls

Derating matters: Always use worst-case datasheet parameters (max V_CE(sat), min f_sw, worst-case T_j)—not typical values.
Layout impact: Stray inductance increases voltage overshoot, raising E_off. Keep gate and power loops tight; use low-inductance busbars.
Thermal interface: Apply TIM with controlled dispensing (e.g., stencil or jetting); avoid air gaps or excessive squeeze-out.
Transient vs. steady-state: Short-term overload (e.g., 150% for 60 s) must be evaluated using thermal capacitance models—not just steady-state resistance.

Frequently Asked Questions

Q1: Can I use natural convection heatsinks for a 5 kW inverter?
Yes—if switching frequency is ≤ 4 kHz, ambient temperature stays below 35 °C, and enclosure volume permits large-fin-area aluminum extrusions (≥ 0.3 m²). However, forced air typically enables 30–50% smaller heatsinks and better derating margin.

Q2: How does gate resistor value affect switching loss?
Increasing gate resistance (R_G) slows turn-on/turn-off, reducing dV/dt and di/dt, but increases switching time—and thus E_on and E_off. Optimize R_G using double-pulse testing to balance loss, EMI, and voltage overshoot.

Q3: Why does heatsink thermal resistance depend on airflow direction?
Vertical airflow (bottom-to-top) leverages natural convection assist and avoids recirculation. Horizontal airflow often suffers from stagnation zones behind fins. CFD modeling or wind-tunnel testing validates optimal orientation and duct geometry.