LLC Resonant Converter Design with the L6599 Controller

The LLC resonant converter has become the topology of choice for high-efficiency, high-power-density AC–DC power supplies in datacenter servers, telecom rectifiers, and USB-C PD adapters. Its ability to achieve zero-voltage switching (ZVS) across wide load and line ranges—combined with low EMI and reduced switching losses—makes it especially compelling for 100–3000 W applications. At the heart of many production-grade LLC designs lies STMicroelectronics’ L6599AD, a dedicated dual-gate driver and resonant controller optimized for half-bridge LLC operation. This article walks through a complete, practical design methodology—from resonant tank synthesis to synchronous rectification—using the L6599 as the control engine.

Why LLC? Why L6599?

Unlike hard-switched PWM topologies, the LLC converter uses a resonant network (inductor–inductor–capacitor) to shape current and voltage waveforms, enabling soft switching over nearly the entire operating range. The L6599 integrates critical functions required for robust LLC operation: precise dual-channel gate drivers with adaptive dead-time control, frequency modulation (FM) up to 1 MHz, built-in overcurrent protection (OCP), adjustable soft-start, and a high-gain error amplifier compatible with optocoupler or digital feedback loops.

Crucially, the L6599 features asymmetric duty-cycle capability and frequency-to-voltage conversion (via its FB pin), allowing direct mapping of output regulation error into resonant frequency—simplifying loop compensation and eliminating need for external FM modulators.

Resonant Tank Design Fundamentals

The LLC tank comprises three passive components: magnetizing inductance (L_m), series inductance (L_r), and resonant capacitance (C_r). Their ratios define key performance boundaries:

Resonant frequency: f_r = 1 / (2π√(L_rC_r)) — sets upper bound of operating frequency.
Characteristic impedance: Z_r = √(L_r/C_r) — determines peak gain and current stress.
Magnetizing ratio: n = L_m/L_r — governs light-load ZVS capability and gain flatness.

Design begins by selecting f_r ≈ 100–250 kHz (balancing magnetics size vs. MOSFET switching loss). Next, compute required gain range from worst-case input (e.g., 90 VAC) and full-load output (e.g., 12 V/100 A). Using normalized gain curves (see below), choose n and L_r/C_r to ensure minimum gain ≥ 1 at maximum input and maximum gain ≤ 1.4–1.6 at minimum input—while maintaining ZVS down to ~10% load.

Understanding Gain Curves & Frequency Modulation

The LLC’s voltage gain M(f) is a function of normalized frequency f/f_r and two dimensionless parameters: n = L_m/L_r and Q = R_ac/Z_r (where R_ac is reflected load resistance). For a fixed n, higher Q (i.e., lighter load) yields lower gain; lower Q raises peak gain but narrows ZVS region.

The L6599 implements pure frequency modulation: output voltage error adjusts switching frequency f_sw inversely—higher error → lower f_sw → higher gain. Typical operating band spans f_min = 0.6–0.7 f_r (full load, high line) to f_max = 0.95–1.05 f_r (light load, low line).

Achieving Robust Soft Switching

ZVS is achieved when the lagging-leg MOSFET’s body diode conducts prior to turn-on—ensuring drain voltage has decayed to near zero. This requires sufficient circulating current in the tank during dead time. Key enablers:

Adequate magnetizing inductance: Ensures residual current flows through L_m even at light loads.
Optimized dead time: L6599’s internal dead-time generator (adjustable via RT/CT pins) must be set to 150–300 ns—long enough for voltage reversal, short enough to minimize conduction loss.
Low-output-capacitance MOSFETs: Critical for fast discharge; SiC FETs are increasingly preferred for >300 V bus applications.

ZCS occurs naturally in the leading leg at turn-off due to resonant current zero-crossing—reducing turn-off loss significantly.

Synchronous Rectification Integration

For secondary-side efficiency >96%, synchronous rectification (SR) is mandatory. The L6599 does not drive SR directly—but its well-controlled square-wave primary waveform enables reliable SR timing. Two approaches dominate:

Voltage-mode sensing: Use fast optocouplers or isolated gate drivers (e.g., Silicon Labs Si823x) triggered by secondary winding voltage polarity.
Current-mode sensing: Place a small sense resistor in series with each SR FET and use a comparator (e.g., TI UCC24612) with programmable delay to avoid shoot-through.

For server PSUs targeting 12 V output, 40–60 V-rated 3.5 mΩ GaN HEMTs (e.g., Navitas NV6128) deliver best-in-class conduction and switching performance.

Practical Design Steps (Server PSU Example)

Assume target specs: 90–264 VAC input, 12 V/100 A (1200 W) output, 96% typical efficiency, 100 kHz nominal f_r.

Select transformer turns ratio: With 400 V DC bus (after PFC), choose n_p/n_s = 18 → 22.2 V on secondary at full load (accounting for winding loss).
Calculate reflected load: R_ac = (12 V × 1.1)² / 1200 W ≈ 0.145 Ω (including 10% margin).
Choose Z_r and n: Set Z_r = 0.4 Ω (gives Q ≈ 0.36 at full load); select n = 70 → ensures ZVS down to 5% load per simulation.
Compute L_r, C_r, L_m: With f_r = 100 kHz → L_r = 1.59 µH, C_r = 15.9 nF, L_m = 111 µH.
Configure L6599: Set RT = 22 kΩ, CT = 100 pF → f_max = 500 kHz (internal oscillator limit); program soft-start time via CSS capacitor; connect FB to optocoupler cathode with Type II compensator (R_C = 10 kΩ, C_C = 1 nF, C_P = 100 pF).

Critical Layout & Protection Considerations

High di/dt in the resonant loop demands minimal loop area: place L_r, C_r, and half-bridge MOSFETs in tight formation with ground-plane stitching vias. Gate drive traces must be length-matched and shielded from noisy nodes. The L6599’s OCP pin accepts current-sense voltage from a resistor in the high-side source path—set threshold to trip at 120% of peak resonant current (≈ 45 A for our example).

Performance Comparison: LLC vs. Phase-Shifted Full-Bridge

Parameter	LLC (L6599)	PSFB (UC3875)
ZVS Range	Full load to 5% load (with proper n)	Limited below ~30% load
Peak Efficiency	96.8% @ 1200 W	95.2% @ 1200 W
EMI Signature	Narrowband + low harmonics	Broadband + high dv/dt spikes

Sample L6599 Feedback Loop Initialization (Pseudo-Code)

// L6599-based LLC startup sequence (executed in MCU or analog state machine)
void l6599_init() {
  // 1. Disable outputs via EN pin
  GPIO_SET(EN_PIN, LOW);
  
  // 2. Charge soft-start capacitor (CSS) to ~2.5 V over 20 ms
  TIMER_START(SS_TIMER, 20_ms);
  while (SS_TIMER_ACTIVE) {
    DAC_OUTPUT(CSS_PIN, ramp_up_2V5_in_20ms());
  }
  
  // 3. Enable L6599; wait for internal VCC OK and oscillator lock
  GPIO_SET(EN_PIN, HIGH);
  DELAY_MS(10);
  
  // 4. Ramp FB reference from 0.8 V → 2.5 V over 50 ms to prevent overshoot
  for (int i = 0; i < 50; i++) {
    DAC_OUTPUT(FB_REF_PIN, 0.8 + (i * 0.034));
    DELAY_MS(1);
  }
}

Frequently Asked Questions

Q1: Can the L6599 drive GaN or SiC MOSFETs directly?
Yes—with appropriate gate-drive resistors (typically 2–5 Ω) and negative turn-off bias (−2 V to −5 V) to ensure fast, reliable depletion. External level-shifters (e.g., IXDN family) are recommended for >600 V systems.

Q2: How do I prevent sub-harmonic oscillation at light loads?
Sub-harmonics arise when duty cycle drops below 50% and loop gain exceeds unity. Mitigate by: (a) reducing compensation capacitor in FB network, (b) adding slope compensation via resistor from CT pin to FB, or (c) using L6599A variant with built-in anti-aliasing filter.

Q3: Is transformer leakage inductance part of L_r?
Yes—leakage inductance is intentionally included in L_r design. However, it must be tightly controlled (±10%) and measured at high frequency (100–500 kHz) under small-signal conditions. Excess uncontrolled leakage degrades ZVS margin and increases EMI.