Power Factor Correction Design Guide: From CCM Boost PFC to Bridgeless Totem-Pole

Power Factor Correction Design Guide: From CCM Boost PFC to Bridgeless Totem-Pole

Introduction and IEC 61000-3-2 Overview

Power Factor Correction (PFC) is no longer optional—it’s a regulatory necessity for medium-to-high power AC-DC converters. The IEC 61000-3-2 standard mandates harmonic current limits for equipment with input power above 75 W, classifying devices into Classes A–D. Class D—covering lighting equipment and personal computers—imposes strict limits on 3rd through 39th harmonics. Without PFC, diode bridge rectifiers feeding bulk capacitors draw highly distorted, peaky current waveforms, resulting in power factor (PF) values as low as 0.5–0.6 and THD exceeding 100%. This not only violates compliance but also stresses utility infrastructure, increases distribution losses, and reduces system capacity. Modern PFC stages serve dual roles: enforcing sinusoidal line current alignment with voltage *and* generating a stable, regulated DC bus (typically 380–400 V) for downstream converters. As efficiency targets climb beyond 95% and form factors shrink, designers are migrating from legacy continuous conduction mode (CCM) boost topologies toward higher-performance alternatives—including bridgeless totem-pole architectures enabled by wide-bandgap devices.

CCM Boost PFC Fundamentals

The CCM boost converter remains the industry workhorse for universal-input (90–264 V_RMS) PFC applications from 200 W to 3 kW. Operating in continuous conduction mode ensures low output ripple, predictable EMI behavior, and high PF (>0.99). Its simplicity—a single inductor, switch (MOSFET), diode, and output capacitor—lends itself to robust control using average-current-mode (ACM) or peak-current-mode (PCM) techniques. In ACM, a multiplier circuit shapes the current reference proportional to the instantaneous rectified sine wave; the error amplifier then forces inductor current to track this reference. Key design considerations include minimizing conduction loss in the boost diode (often addressed with SiC Schottky diodes), managing MOSFET switching loss at high frequency (typically 65–135 kHz), and ensuring stable loop response across full load and line ranges. Thermal management of the main switch and diode becomes critical above 500 W, where junction temperatures can exceed 125°C without careful layout and heatsinking.

DCM and CrCM Boundary Conduction

Discontinuous conduction mode (DCM) and critical conduction mode (CrCM, or boundary mode) offer compelling trade-offs for lower-power applications (<300 W) or cost-sensitive designs. In DCM, the inductor current falls to zero each switching cycle, eliminating reverse-recovery loss in the output diode—a major advantage over CCM when using silicon diodes. However, DCM suffers from higher peak currents, increased RMS conduction losses, and variable switching frequency that complicates EMI filter design. CrCM operates precisely at the boundary between CCM and DCM, maintaining zero-current switching (ZCS) for the diode while keeping peak current lower than pure DCM. Controllers like the UCC2800 series implement valley-switching detection to trigger the MOSFET at the natural inductor current zero-crossing, enabling soft switching and reducing electromagnetic interference. While CrCM simplifies magnetics design (smaller inductors possible), its variable-frequency operation requires wider bandwidth EMI filters and complicates multi-phase synchronization.

Interleaved PFC with UCC28070

For systems demanding >1 kW with low ripple and high efficiency, interleaved CCM PFC provides significant advantages. By phase-shifting two or more identical boost cells (typically 180° for dual-phase), input and output current ripples cancel, reducing RMS current stress on input capacitors and bulk storage. Output voltage ripple drops quadratically with phase count—e.g., dual-phase cuts ripple by ~70% versus single-phase. The TI UCC28070 is a dedicated dual-phase interleaved PFC controller supporting both average-current and voltage-mode control. It integrates phase-shifted PWM generation, cycle-by-cycle current limiting, and built-in fault protection (overvoltage, overcurrent, overtemperature). Interleaving also distributes thermal load across multiple switches and inductors, improving reliability and enabling smaller passive components. Drawbacks include higher component count (two inductors, two MOSFETs, two diodes), complex PCB layout to maintain symmetry, and sensitivity to mismatched parasitics—requiring careful gate drive routing and current-sense calibration.

Bridgeless Totem-Pole with GaN HEMTs

The bridgeless totem-pole PFC topology eliminates the front-end diode bridge entirely, replacing it with two active switches (high-side and low-side) per leg and two unidirectional conduction paths. During positive half-cycles, the low-side switch conducts while the high-side switch is modulated; during negative half-cycles, roles reverse. This architecture slashes conduction losses by ~40% compared to conventional boost—since only one active device and one body diode (or synchronous FET) carry current per half-cycle, avoiding four-diode bridge drop (≈2.8 V). To realize this benefit, fast, low-Q_rr switches are essential: GaN HEMTs excel here due to near-zero reverse recovery charge (Q_rr ≈ 0), ultra-low gate charge (Q_g), and sub-100 ns switching transitions. Controllers such as the NCP1680 and ICE5QSBG support high-frequency (≥150 kHz) totem-pole operation with adaptive dead-time control and precise zero-voltage switching (ZVS) detection. Thermal design must account for asymmetrical power dissipation—low-side switches typically handle higher average current—and layout must minimize common-source inductance to preserve switching fidelity.

Inductor and Magnetics Design

The boost inductor is arguably the most critical passive component in any PFC stage—dictating size, loss, saturation margin, and EMI signature. Its value determines conduction loss (I²R), core loss (frequency- and flux-density-dependent), and audible noise (mechanical vibration at switching or line frequency). Inductor design begins with establishing ripple current ΔI, typically set to 20–40% of peak line current for optimal trade-off between copper loss and core volume. For a CCM boost operating at minimum input voltage (V_{in_min}), output voltage (V_out), switching frequency (f_sw), and desired ripple (ΔI), the required inductance is:

L = (Vin_min^2 * (Vout - Vin_min)) / (ΔI * f_sw * Vout)

This equation assumes ideal duty cycle derivation and neglects winding resistance and fringing effects—but serves as an accurate first-order estimate. Core selection balances saturation flux density (B_sat), core loss coefficient (k_i), and effective area (A_e). Powdered iron cores offer high saturation but higher core loss; gapped ferrites provide lower loss at high frequency but require careful gap optimization to avoid excessive fringing flux. Winding technique—bifilar, litz wire, or foil—must address skin and proximity effects, especially above 100 kHz. Finally, thermal derating is non-negotiable: inductors should be rated for ≥40°C ambient rise at full load, with surface temperature monitored during validation.

Real Efficiency Curves and SiC Diode Benefits

Published efficiency curves often mask real-world compromises. A typical 650 V, 20 A SiC Schottky diode (e.g., C3D02060E) reduces conduction loss by ~40% versus a fast-recovery silicon diode—cutting forward voltage drop from 1.4 V to 1.7 V at 25°C, with negligible temperature dependence and zero reverse recovery. When paired with a 650 V silicon MOSFET in a CCM boost, measured efficiency gains range from 0.3% at 230 V/100% load to over 0.8% at 90 V/20% load—where conduction loss dominates. In contrast, GaN-based totem-pole designs achieve >98.5% peak efficiency at 1 kW, with flat efficiency curves across 10–100% load thanks to reduced switching and conduction losses. Real-world measurements show SiC diodes enable >10°C cooler operation at the output rectifier node, directly extending electrolytic capacitor lifetime. Moreover, their faster turn-off suppresses high-frequency ringing, easing EMI filter requirements and reducing common-mode noise coupling.

Conclusion

PFC design has evolved far beyond “just adding a boost converter.” From foundational CCM boost implementations to advanced bridgeless totem-pole topologies leveraging GaN and SiC, the path to high efficiency, small size, and regulatory compliance demands deep understanding of trade-offs across power range, cost, control complexity, and thermal performance. CCM boost remains ideal for cost-sensitive, mid-power applications where proven reliability and simple control outweigh marginal efficiency gains. CrCM bridges the gap for compact adapters and LED drivers. Interleaving unlocks scalability and ripple reduction for server PSUs and industrial supplies. And bridgeless totem-pole—now commercially viable with robust GaN drivers and integrated controllers—sets the benchmark for next-generation high-density, high-efficiency AC-DC conversion. Regardless of topology, magnetics design, thermal management, and EMI mitigation remain foundational disciplines. As wide-bandgap devices mature and controller intelligence increases, the future of PFC lies not in incremental improvement—but in redefining what’s physically and economically possible in power conversion.