Phase-Shifted Full-Bridge DC-DC Converter Design and Analysis
The phase-shifted full-bridge (PSFB) converter stands as a cornerstone topology in medium-to-high-power isolated DC-DC applications—especially where efficiency, thermal management, and EMI performance are critical. Widely deployed in telecom rectifiers, server PSUs, EV battery chargers, and industrial power supplies (3–10 kW range), the PSFB leverages soft-switching to overcome limitations of conventional hard-switched full-bridge converters. This article provides a rigorous yet accessible technical deep dive into its operating principles, design trade-offs, component selection, and practical implementation considerations.
Operating Principle and Topology Overview
The PSFB comprises four primary MOSFETs arranged in a full-bridge configuration driving an isolation transformer, followed by a center-tapped or full-wave rectifier and output filter. Unlike traditional PWM-controlled bridges that modulate duty cycle symmetrically, the PSFB fixes each leg’s duty cycle at approximately 50% and introduces a controllable phase shift between the gate drive signals of the leading-leg (Q1, Q4) and trailing-leg (Q2, Q3) switches. This phase difference—denoted as φ—directly regulates output voltage.
For a nominal input voltage Vin, turns ratio n = Np/Ns, and phase shift angle φ (normalized to switching period Ts), the ideal output voltage is:
V_out ≈ (V_in / n) × (φ / T_s)Operation occurs across five distinct intervals per half-switching cycle, governed by resonant tank behavior formed by transformer leakage inductance (Llk), magnetizing inductance (Lm), and parasitic capacitances. Crucially, zero-voltage switching (ZVS) is achieved for all four switches under proper design conditions—enabling dramatic reductions in switching losses and EMI generation.
ZVS Soft-Switching Mechanism
ZVS in the PSFB relies on energy stored in the resonant tank to discharge switch output capacitances (Coss) before turn-on. For leading-leg switches (Q1, Q4), ZVS is relatively robust: during dead time, current through the magnetizing inductor circulates via body diodes, naturally discharging the opposite switch’s Coss.
Trailing-leg ZVS is more sensitive—it requires sufficient circulating current to fully discharge Coss before gate drive activates. This demands careful tuning of Lm and minimum load current. Below a critical load threshold, trailing-leg ZVS may collapse, reverting to hard switching and increasing losses. Design guidelines recommend maintaining peak magnetizing current ≥ 1.5× the minimum required ZVS current, typically calculated as:
I_ZVS_min ≈ √(2 × C_oss × V_in² / L_m)Where Coss is the effective output capacitance per switch at Vin. This constraint directly influences transformer design and minimum load specification.
Phase-Shift PWM Control Strategy
Modern PSFB controllers (e.g., UCC28950, LM5041) implement digital or analog phase-shift modulation with programmable dead time, adaptive slope compensation, and current-mode or voltage-mode feedback. The control loop adjusts φ to regulate output voltage while preserving fixed 50% duty cycles—minimizing transformer core loss and simplifying gate driver timing.
A typical firmware-based control snippet (simplified C pseudo-code) illustrates real-time phase adjustment:
// PSFB phase-shift control loop (simplified)
float vout_measured = read_adc(OUT_VOLTAGE);
float error = vref - vout_measured;
float phi_corr = pid_compute(&vout_pid, error);
// Clamp phase shift between min/max bounds
phi_cmd = clamp(phi_base + phi_corr, PHI_MIN, PHI_MAX);
// Update PWM compare registers for trailing leg
PWM_TRIG_LEADING = 0; // Fixed leading edge
PWM_TRIG_TRAILING = (uint16_t)(T_PERIOD * phi_cmd / T_PERIOD_MAX);
// Enforce minimum dead time (e.g., 200 ns)
set_dead_time(DEAD_TIME_MIN);This architecture enables fast transient response while avoiding shoot-through risks inherent in variable-duty-cycle schemes.
Duty Cycle Loss and Voltage Gain Limitation
A key non-ideal effect in PSFB operation is duty cycle loss: due to finite switch transition times and dead time requirements, the effective duty cycle delivered to the transformer is less than 50%. More critically, the achievable voltage gain is reduced at light loads because ZVS margin shrinks, forcing the controller to limit minimum φ—thus capping minimum output voltage. The practical gain equation becomes:
V_out / V_in ≈ (1/n) × (φ − φmin) / (1 − φmin)
where φmin represents the smallest usable phase shift before ZVS failure. Designers mitigate this by selecting devices with low Coss, optimizing transformer leakage, and using auxiliary circuits (e.g., active clamps or synchronous rectification) to extend regulation range.
Transformer and Output Inductor Design
The PSFB transformer must simultaneously support ZVS operation and minimize conduction loss. Key parameters include:
- Magnetizing inductance (Lm): Sized to ensure ZVS across full load range—typically 3–5× the reflected output inductance.
- Leakage inductance (Llk): Intentionally controlled (often via interleaved windings or air gaps) to form resonant tank with Coss. Target: 2–6% of Lm.
- Winding arrangement: Interleaving primary/secondary layers reduces AC resistance and leakage variance.
The output filter inductor operates in continuous conduction mode (CCM) with ripple current ΔIL ≈ 20–30% of Iout_max. Its value is derived from:
L_out = (V_out × (1 − V_out/V_in_eff)) / (f_sw × ΔI_L)where Vin_eff accounts for duty loss and transformer turns ratio. Core selection prioritizes low core loss at high frequency (e.g., ferrite N87/N97) and adequate saturation margin.
Snubber Design Considerations
While ZVS suppresses most switching loss, voltage spikes from leakage inductance reset and diode reverse recovery still require mitigation. A passive RCD snubber across the primary is common—but adds conduction loss. Alternatively, a lossless passive snubber (e.g., active clamp or resonant reset) recycles energy into the input bus or output rail. For cost-sensitive designs, a well-damped RC network across each switch (R = 10–100 Ω, C = 1–10 nF) suffices for EMI compliance without excessive loss.
Comparison with Hard-Switched Full-Bridge
The PSFB’s advantages stem almost entirely from soft-switching. The table below compares key characteristics:
| Parameter | Hard-Switched FB | Phase-Shifted FB |
|---|---|---|
| Switching Losses | High (proportional to fswVinIsw) | Low (ZVS reduces turn-on loss to near zero) |
| EMI Profile | Broadband, high dv/dt peaks | Narrower spectrum, lower peak dv/dt |
| Control Complexity | Simple PWM, fixed phase | Requires precise phase alignment & dead-time management |
| Light-Load Efficiency | Moderate (switching loss dominates) | High—provided ZVS is maintained |
| Design Margin Sensitivity | Low (robust but inefficient) | High (Lm, Coss, layout parasitics critically affect ZVS) |
Practical Design Checklist
- Verify ZVS condition across entire load and line range using worst-case Coss and Lm tolerances.
- Select MOSFETs with low Qg and Coss, matched Rds(on), and robust body diodes.
- Minimize PCB loop inductance—especially gate drive and primary power paths—to preserve ZVS timing integrity.
- Implement adaptive dead-time control if using microcontroller-based drivers.
- Validate transformer parasitics with impedance analyzer or calibrated SPICE model before prototyping.
Frequently Asked Questions
Q1: Can PSFB operate at unity voltage gain?
No—unity gain (Vout = Vin/n) requires φ = Ts/2, which is physically impossible due to dead time and ZVS constraints. Practical maximum gain is ~0.85–0.92× theoretical maximum, depending on device selection and layout.
Q2: Why does the PSFB often use center-tapped secondary rectification?
Center-tapped secondaries reduce diode voltage stress (to Vin/n) and halve conduction loss compared to full-bridge rectifiers—critical for high-current, low-voltage outputs. Synchronous rectification further improves efficiency but adds control complexity.
Q3: Is PSFB suitable for wide-input-range applications (e.g., 200–400 Vdc)?
Yes—with caveats. Input variation affects ZVS margin and voltage stress. Designers often employ adaptive Lm control (via auxiliary winding or variable inductance) or hybrid modulation (phase-shift + burst mode) to maintain efficiency across the range.