STM32 Advanced Timer PWM Configuration for Full-Bridge Inverters
Configuring the STM32 advanced-control timers (TIM1 and TIM8) for power electronics applications requires careful attention to dead-time insertion, complementary output generation, and break protection. This article presents a production-tested configuration extracted from a 750W single-phase full-bridge inverter project based on the STM32F103, demonstrating both inverter-leg PWM generation using TIM1 and boost PFC control using TIM8.
1. STM32 Advanced Timer Overview
The STM32F103 advanced-control timers (TIM1 and TIM8) are purpose-built for motor control and power conversion applications. Unlike general-purpose timers, they offer:
- Complementary outputs with programmable dead-time — critical for half-bridge and full-bridge topologies to prevent shoot-through
- Break input for hardware fault shutdown with automatic output disable
- Center-aligned counting modes that naturally produce symmetric PWM, reducing harmonic distortion
- Shadow register preload (ARR and CCRx) to ensure synchronous duty cycle updates within a single PWM period
In this design, TIM1 drives the full-bridge inverter stage and TIM8 controls the interleaved PFC boost converter, both operating at a 32 kHz carrier frequency from a 72 MHz system clock.
2. Center-Aligned PWM with Dead-Time Configuration
The inverter full-bridge employs TIM1 with complementary CH1+CH1N outputs for one leg. The carrier period is calculated as:
f_carrier = TIM1_CLK / (ARR + 1) / 2 = 72 MHz / 1125 / 2 ≈ 32 kHz
where ARR = INV_CARRIER_PRDDead-time is configured through the TIM_BDTRInitStructure register block. The dead-time value of 84 corresponds to:
t_dead = TIM_DeadTime × t_DTS = 84 × (1 / 72 MHz) = 84 × 13.89 ns ≈ 1.16 µsThis 1.16 µs dead-band provides a safe margin for the IGBT/MOSFET turn-off delay while minimizing conduction losses from body-diode freewheeling.
3. Complementary Outputs and Break Protection
The complementary output configuration sets both the primary and complementary channels active with high-polarity outputs and reset-state idle values:
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;The break function is enabled with active-low polarity and automatic output re-enable:
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_Low;
TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;When the break input (BKIN pin) is pulled low, both TIM1 outputs are immediately forced to their idle states, providing hardware-level over-current protection independent of software interrupt latency. The TIM_AutomaticOutput_Enable flag allows the outputs to recover automatically once the break condition clears, without requiring software intervention.
4. Three-Level Modulation via PWM Mode Selection
A notable design technique in this codebase is the use of both TIM_OCMode_PWM1 and TIM_OCMode_PWM2 on different channels of the same timer to implement a three-level, five-segment SVPWM pattern. Channel 1 (CH1+CH1N) uses PWM1 mode for the primary switching, while Channel 2 uses PWM2 mode:
// Channel 1: PWM1 — active high when CNT > CCR1
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_Pulse = 0;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
// Channel 2: PWM2 — active high when CNT < CCR2
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
TIM_OCInitStructure.TIM_Pulse = INV_CARRIER_PRD;
TIM_OC2Init(TIM1, &TIM_OCInitStructure);By combining PWM1 on CH1 (lower switch) with PWM2 on CH2 (upper clamping switch), the three-level NPC topology generates five distinct voltage levels per switching cycle: +Vdc, +Vdc/2, 0, -Vdc/2, -Vdc. This reduces output voltage THD compared to traditional two-level modulation.
| Parameter | TIM1 (Inverter) | TIM8 (PFC Boost) |
|---|---|---|
| Counting Mode | Center-Aligned (Up) | Center-Aligned 3 |
| Dead-Time | 84 (1.16 µs) | 42 (0.58 µs) |
| Carrier Frequency | 32 kHz | 32 kHz |
| Break Polarity | Active Low | Active Low |
| Output Mode | Complementary CH1+CH1N | Complementary CH1+CH1N |
5. PFC Boost Converter Configuration (TIM8)
TIM8 is configured for the PFC boost stage with a center-aligned 3 counting mode (TIM_CounterMode_CenterAligned3). This mode produces a three-level modulation pattern where the compare match triggers the output at both the up-count and down-count compare events, effectively doubling the ripple frequency seen by the inductor — a technique known as frequency doubling in interleaved PFC.
The PFC stage uses a shorter dead-time of 0.58 µs (TIM_DeadTime = 42), since the boost IGBT typically switches faster than the inverter-stage devices and the current levels are lower during light-load conditions.
6. Shadow Register Preload and Safe Debugging
Both timer configurations enable the auto-reload preload (TIM_ARRPreloadConfig) and compare preload (TIM_OC1PreloadConfig / TIM_OC2PreloadConfig) registers. This ensures that all duty cycle and period updates are applied synchronously at the next update event (UEV), preventing partial updates that could cause asymmetric PWM cycles and DC current injection into the transformer or grid.
A BOARD_TEST_MODE preprocessor macro gates a safety mechanism that keeps all PWM outputs disabled unless the macro is explicitly defined:
#ifndef BOARD_TEST_MODE
TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable);
#else
TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable);
#endifThis is an essential practice for power electronics firmware: the default compilation does not enable power-stage outputs. Developers must consciously define BOARD_TEST_MODE before any hardware testing can begin.
7. Practical Design Recommendations
- Dead-time calculation: Always verify with an oscilloscope. Factor in gate-driver propagation delay (typically 50–100 ns) and IGBT/MOSFET datasheet turn-off delay. Add at least 50% margin.
- Break filtering: The STM32 break input is level-sensitive. Use an external RC filter (e.g., 1 kΩ + 1 nF) to prevent noise-triggered shutdowns in high-EMI environments.
- Shadow register coordination: When updating multiple duty cycle registers per PWM cycle, use the TIM update event as a synchronization point. Write all CCRx values before the next update event arrives.
- Center-aligned selection: Use
TIM_CounterMode_CenterAligned1when you need the update event at the counter overflow (top of triangle). UseTIM_CounterMode_CenterAligned3when the update event should occur at both overflow and underflow for double-update-rate control loops.