Q: What are the key DDR3/DDR4 PCB layout guidelines for STM32 and H7 MCUs?
Answer
DDR3/DDR4 on STM32H7 requires careful impedance control: single-ended traces 50 Ohm +-10% differential pairs 100 Ohm +-10%. Match byte-lane lengths to +-1.27 mm (50 mil). Address/command/control signals should be length-matched within each group. VREF trace width 0.5 mm with 100 nF decoupling cap nearby. Use a continuous ground plane under all DDR signals – never route DDR over split planes. Use fly-by topology for DDR3 address signals to multiple chips with appropriate ODT termination at the last chip. Keep DQS pairs within +-0.25 mm of their corresponding DQ bits. Minimize via count (<=2 per signal). SI simulation with HyperLynx or ADS is recommended for 400+ MHz DDR3L.
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