30 kW Bidirectional Energy-Storage PCS: T-Type Three-Level Topology, DSP Control and System Design
This article presents a comprehensive technical analysis of the CPS ECB 30KTL-O/US, a 30 kW bidirectional energy-storage power conversion system (PCS) developed by Chint Power Systems. Based on production-grade hardware schematics, TI C2000 DSP firmware, and algorithm documentation dated October 2016 (with subsequent RULE21 compliance updates in February 2019), this design exemplifies industrial-grade implementation rigor for grid-tied and off-grid battery storage applications. The architecture integrates a dual-stage power flow path—comprising a T-type three-level inverter stage and a four-phase interleaved bidirectional DC–DC stage—controlled entirely in fixed-point arithmetic on the TMS320F28235 DSP. This analysis details topology selection rationale, gate-driver isolation strategy, real-time control loop structure, neutral-point balancing methodology, and regulatory adaptation mechanisms, providing engineering insight into high-fidelity, production-ready PCS design.
System Architecture and Operational Modes
The CPS ECB 30KTL-O/US implements a two-stage topology to decouple battery interface dynamics from grid synchronization requirements. This architectural choice enables independent optimization of voltage gain range (via DC–DC) and harmonic performance (via multi-level inversion), while preserving full bidirectional power flow capability across four quadrants of the P–Q plane.
In grid-tied discharge mode, energy flows from the battery pack through the bidirectional DC–DC stage operating in boost configuration, elevating the battery voltage (typically 200–900 VDC) to a regulated split DC bus (~750 VDC differential). From there, the T-type three-level inverter synthesizes sinusoidal 230/400 VAC (50/60 Hz) output synchronized to the utility grid via PLL. In grid-tied charge mode, the inverter operates as a three-level active rectifier—drawing AC power from the grid, converting it to DC, and regulating the split bus voltage; the DC–DC stage then operates in buck mode to deliver controlled charging current to the battery.
For off-grid (islanding) operation, the inverter transitions to voltage-source mode using V/f control. It autonomously establishes and regulates AC output voltage magnitude and frequency, enabling seamless backup power delivery without grid reference. The system supports programmable reactive power injection (±100% of rated apparent power) and dynamic power factor adjustment (0.95 leading to 0.95 lagging), essential for microgrid stability and utility support functions.
A critical enabler of this operational flexibility is the split DC bus architecture: BUS+, BUS-N (neutral), and PV-Neg (negative rail). Unlike conventional two-rail systems, this three-rail configuration provides inherent symmetry for neutral-point clamping and allows independent monitoring of upper-bus (BusHVolt+/BusHVolt−) and lower-bus (BusLVolt+/BusLVolt−) voltages. This dual-voltage sensing forms the foundation for both closed-loop bus regulation and real-time neutral-point potential balancing—a non-negotiable requirement for reliable T-type operation.
T-Type Three-Level Inverter Stage: Topology and Hardware Implementation
The inverter stage employs a T-type neutral-point-clamped (T-type NPC) topology, selected over diode-clamped (NPC) or flying-capacitor variants for its superior efficiency, reduced component count, and simplified thermal management. Each phase leg comprises four switching devices: two outer 1200 V IGBTs and two inner 650 V IGBTs configured in a “T” formation, eliminating the need for bulky, lossy clamping diodes found in classical NPC designs.
| Function | Device | Key Parameters | Quantity (per phase / total) |
|---|---|---|---|
| Outer Switches | FGH40T120SMD | 1200 V / 40 A, SMD package, low Eoff | 4 / 12 |
| Neutral-Clamping Switches | STGW60H65FB | 650 V / 60 A, trench field-stop, integrated FWD | 2 / 6 |
| Clamping Diodes | IDW40E65D1 | 650 V / 40 A, ultrafast recovery (trr < 50 ns) | 2 / 6 |
| Gatedriver IC | ACPL-332J + TLP5214 | Galvanic isolation (5 kVRMS), DESAT detection, Miller clamp | 4 / 12 |
The gate-drive subsystem exemplifies robust industrial design. Each phase receives fully isolated ±15 V drive power generated by a dedicated UC2845BD1 current-mode PWM controller driving an FDS5672 MOSFET, coupled to a custom T-SCA30K-T02 high-frequency transformer. This yields six independent, noise-immune drive rails—one per outer switch and one per clamping switch—critical for preventing shoot-through during high-dv/dt commutation. Gate resistors are meticulously engineered: a 10 Ω series resistor with parallel 332 Ω (for turn-off damping) and a 5.11 kΩ pull-down ensures controlled turn-on/turn-off dV/dt and suppresses Miller-induced false triggering. Negative voltage turn-off (VEE1A, VEE34A) further enhances noise immunity.
Switching losses and EMI are mitigated through a layered snubbing strategy. Each IGBT collector-emitter node features a 220 pF / 2 kV ceramic capacitor for high-frequency oscillation suppression, while bulk 100 nF / 630 VDC film capacitors provide low-impedance paths for switching current transients. The AC output employs an LCL filter (inductor–capacitor–inductor) with coordinated relay sequencing (sRelayDelayDeal) to ensure zero-current make/break during grid connection/disconnection, satisfying IEEE 1547 anti-islanding requirements.
Four-Phase Interleaved Bidirectional DC–DC Stage
The DC–DC stage realizes a four-phase interleaved bidirectional Buck/Boost converter, connecting the battery to the split DC bus. Interleaving reduces input and output current ripple by a factor of ~4× compared to a single-phase implementation, directly translating to smaller passive components, lower conduction losses, and reduced acoustic noise. With 16 total FGH40T120SMD IGBTs (4 per phase × 4 phases), the stage delivers up to 30 kW at >98.2% peak efficiency.
Control logic dynamically optimizes efficiency across the load range. Under light-load conditions, the system executes sDC12And34OptSwitch—a software-controlled reconfiguration that disables two interleaved legs (phases 1&2 or 3&4), reducing switching losses and gate-drive power consumption. This adaptive topology switching maintains >95% efficiency down to 5% of rated power. The control loop employs a cascaded structure: an outer voltage loop regulates either battery voltage (charge mode) or DC bus voltage (discharge mode), while inner current loops (swBiDirectionalDCCurrCtr1st–4th) enforce precise current tracking. Phase-shifted PWM generation ensures natural current sharing and minimizes circulating currents between phases.
Crucially, the DC–DC and inverter stages share the same DC bus voltage sensing infrastructure. This tight coupling simplifies system calibration and enables fast cross-stage coordination during mode transitions—for example, when exiting a grid fault, the DC–DC stage rapidly adjusts its reference to assist the inverter in restoring bus voltage before resuming active power transfer.
DSP-Based Real-Time Control Architecture
All control algorithms execute on the TMS320F28235 DSP—a 150 MHz, 32-bit fixed-point processor from Texas Instruments’ C2000 family. Notably, the design foregoes floating-point units (FPU), relying instead on rigorous Q-format arithmetic for deterministic timing and memory efficiency. Key scaling constants are defined in Q14 (e.g., cSqrt3 = 28378, representing √3 ≈ 1.7320508) and Q20 (e.g., cPLLFreqAngleGain = 42723). This approach eliminates floating-point library overhead and guarantees worst-case execution time bounds essential for safety-critical power electronics.
The software architecture is organized into modular, interrupt-driven functional units:
- Main Control Interrupt (
sInvController): Executes every 125 µs (8 kHz) in base firmware; upgraded to 62.5 µs (16 kHz) for RULE21 compliance. This high-priority ISR orchestrates coordinate transformations, PI regulator updates, and SVPWM duty-cycle computation. - PLL Engine (
sPLLControl): Implements a Type-II digital PLL using a 720-point sine lookup table. Frequency tracking bandwidth is set to 10 Hz, with adaptive gain scheduling to maintain lock during grid disturbances. Angle estimation uses Q20 arithmetic to preserve resolution at low frequencies. - Clarke/Park Transforms: All forward and inverse transforms use Q14 constants. The Park transformation rotates the stationary αβ-frame currents into the rotating dq-frame, where decoupled PI regulators (
cDCCurrKp = 1086,cDCCurrKi = 2) independently control active (d-axis) and reactive (q-axis) current components.
A key innovation lies in the three-level Space Vector PWM (SVPWM) generator (sSVModu). Unlike two-level modulation, T-type SVPWM must resolve seven valid voltage vectors per sector (including zero vectors) and manage neutral-point voltage drift. The algorithm performs sector identification using three linear discriminants (Ubeta, Ubeta + sqrt3*Ualfa, Ubeta - sqrt3*Ualfa), then computes vector action times Ta, Tb, Tc normalized to the switching period Ts. Neutral-point balancing is achieved by injecting a corrective weighting factor (wFactor1 + wFactor2 = 0x7FFF in Q15) that modulates the dwell times of positive and negative small vectors based on instantaneous neutral-point current polarity—ensuring long-term bus voltage symmetry without auxiliary hardware.
Comprehensive Protection and Regulatory Compliance
Safety and reliability are enforced through a multi-layered protection architecture spanning hardware, firmware, and system levels. Hardware protections include analog comparators (LM2903) for immediate bus overvoltage (BUSOVP) shutdown and discrete DESAT detection circuits in each ACPL-332J driver. These trigger hardware-level fault latching within nanoseconds, disabling all gate drivers via the global InvDrvPwrEN signal.
Firmware-level protections, implemented in PROTECT.c (141 KB), monitor over 20 parameters—including DC bus voltage imbalance (>15 V differential), phase current asymmetry (>12 A difference), heatsink temperature (>85 °C), and grid frequency deviation (>±0.5 Hz). All protections employ hysteresis and debouncing to prevent nuisance tripping during transient events.
The system achieves full compliance with California’s stringent RULE21 interconnection standard through targeted firmware modifications. The PCS_30kVA_16kHz_RULE21_20190227 build introduces:
- Enhanced Low-Voltage Ride-Through (LVRT) logic (
sCalLVRTReactivePowerRef) that injects reactive current proportional to voltage sag depth; - Voltage and frequency trip thresholds tightened to ±2% and ±0.1 Hz respectively;
- Fast-reactive-power response (<500 ms) during faults;
- Grid-support functions including ramp-rate limiting and configurable reactive power vs. voltage (Q(V)) curves.
This regulatory adaptation demonstrates how deeply embedded control logic can be modified without hardware changes—leveraging the DSP’s computational headroom and flexible peripheral configuration.
Design Validation and Simulation Methodology
Algorithm development and verification employed a co-simulation workflow integrating MATLAB/Simulink with production C code. Critical control blocks were implemented as S-functions:
svpwm.c(742 lines): A complete three-level SVPWM model incorporating sector detection, vector timing, dead-time insertion (2.5 µs), and neutral-point balancing logic;VSG.c(419 lines): A virtual synchronous generator model emulating inertia and damping characteristics for microgrid stabilization;BirDirControll.c: A detailed bidirectional DC–DC controller model with interleaved current loops and mode-switching logic.
These models ran at a 125 µs sample rate, matching the target DSP’s interrupt period, and interfaced with high-fidelity Simscape Electrical models of the T-type inverter and DC–DC stages. This enabled closed-loop validation of stability margins, harmonic distortion (THD < 2.5% at full load), and transient response (voltage recovery < 200 ms after 50% step load change) prior to hardware deployment.
Engineering Insights from Production Firmware
1. Fixed-Point Discipline Pays Off: All PI integrators implement anti-windup via back-calculation (cBusSumVoltKaw = 10), preventing integrator saturation during current limits. This avoids overshoot and ensures smooth recovery.
2. Thermal Intelligence: Battery and heatsink temperatures are not merely monitored—they are actively used for derating. swModuleEnvTempFit and swModuleHeatTempFit apply polynomial curve-fitting to NTC sensor data, enabling precise, continuous power derating rather than coarse stepwise reduction.
3. DC Injection Suppression: A dedicated sDciControl module monitors DC current components at multiple thresholds (40 mA, 64 mA, 150 mA). Upon detection, it injects counteracting compensation into the current reference—ensuring compliance with IEEE 1547’s 0.5% DC injection limit.
Partner with InnovChip
The CPS ECB 30KTL-O/US represents more than a reference design—it embodies a mature, production-proven architecture for high-performance, standards-compliant energy storage systems. At InnovChip, we specialize in accelerating your PCS development cycle through deep expertise in multi-level topologies, real-time DSP control, and grid-code compliance engineering.
Whether you require a custom 30–250 kW bidirectional PCS optimized for lithium-ion, LFP, or emerging battery chemistries—or need assistance adapting proven control algorithms (T-type SVPWM, VSG, RULE21 LVRT) to your specific hardware platform—we offer end-to-end engineering services:
- Full schematic and PCB design (Altium Designer)
- TI C2000 DSP firmware development (C/Q-format, CCS)
- Functional safety certification support (IEC 61508 SIL2)
- EMC pre-compliance testing and mitigation
- Regulatory adaptation (UL 1741 SA, IEEE 1547-2018, GB/T 34120)
Let InnovChip’s power electronics engineers translate your system requirements into a robust, certified, and manufacturable solution. Contact our PCS design team today to discuss your next-generation energy storage project.