Key Takeaways
- A bootstrap circuit enables cost-effective high-side gate drive for N-channel MOSFETs/IGBTs in half-bridge topologies by using a flying capacitor charged during low-side conduction — eliminating the need for multiple isolated supplies.
- Bootstrap operation imposes a fundamental duty-cycle limit: the low-side switch must turn on periodically to recharge Cboot; continuous high-side conduction requires auxiliary refresh or alternative supply schemes.
- Dead time is not just a driver specification — it’s an effective timing window shaped by asymmetric propagation delays (e.g., HS turn-off delay of 400 ns vs. LS turn-on delay of 1000 ns), requiring bench validation with actual gate waveforms.
- Shoot-through prevention relies on both hardware interlock logic (which forces both outputs low for invalid input combinations) and correct signal polarity alignment between controller PWM and driver input convention (e.g., complementary HIN/LIN).
- Critical layout practices include minimizing the bootstrap loop area (Cboot, Dboot, VB/VS pins), using Kelvin source connections to suppress VS spikes, and separating logic and power ground return paths to avoid noise coupling.
Half-Bridge Gate Driver and Bootstrap Circuit Design: Dead Time and Shoot-Through Protection
Designing a robust half-bridge power stage hinges on precise gate driving — especially for the high-side switch, where voltage referencing challenges demand careful attention to supply architecture, timing control, and fault resilience. While discrete isolated supplies offer clean performance, they scale poorly in cost, size, and complexity. The bootstrap circuit remains the dominant solution for medium-power applications, delivering floating high-side drive from a single low-voltage supply. However, its simplicity belies nuanced design constraints: duty-cycle limits, parasitic-induced voltage transients, propagation delay mismatches, and subtle logic interface pitfalls that can all culminate in shoot-through failure. This article details how to implement a reliable bootstrap-based half-bridge gate driver — covering component selection, timing analysis, interlock behavior, and layout best practices — all grounded in real IC specifications and field-proven failure modes.
Why a Floating High-Side Driver Channel Is Essential
In a standard half-bridge composed of two N-channel power devices, the lower switch source connects to ground (GND), enabling straightforward gate drive referenced to that fixed potential. The upper switch source, however, connects to the switching node (VS), which swings dynamically between GND and the positive bus voltage (VBUS). To turn the upper device fully on, its gate must be driven ~10–15 V above its source — meaning the gate drive supply must “float” with VS. Without this, the upper gate would be referenced to GND, resulting in insufficient VGS during high bus conditions and incomplete turn-on (high RDS(on), excessive conduction loss, thermal runaway).
Two classical approaches resolve this:
- Dedicated isolated supplies: One per high-side channel (e.g., transformer-coupled or capacitive-isolated DC/DC). Offers excellent noise immunity and unlimited duty cycle but multiplies BOM cost, PCB area, and design effort — particularly prohibitive in full-bridge or multi-phase systems.
- Bootstrap supply: A charge-pump-like network using a diode (Dboot) and capacitor (Cboot) to generate a floating rail (VB) referenced to VS. Requires only one main VCC supply and minimal passive components, making it the go-to for cost-sensitive, space-constrained, and medium-duty-cycle applications (e.g., motor drives, SMPS half-bridges, LED drivers).
The bootstrap method leverages the natural low-side conduction period to replenish energy — turning a constraint (the switching node’s motion) into an enabler. But that dependency also introduces its first critical limitation: it cannot sustain 100% high-side duty cycle.
How the Bootstrap Charging Cycle Works
A typical integrated high-voltage half-bridge driver IC contains two independent output stages sharing one logic supply (VDD) and one power supply (VCC), with separate grounds: VSS (logic ground) and COM (power ground). The high-side channel operates from a floating domain defined by VB (high-side supply) and VS (switching node). A high-voltage level shifter transfers the logic-level input (HIN) across the isolation barrier to control the floating output stage.
The bootstrap sequence unfolds in two phases per switching cycle:
Phase 1: Low-Side On → Bootstrap Capacitor Charging
When LIN = HIGH, the low-side driver pulls LO to VCC (≈12–15 V), turning on the lower MOSFET. This pulls VS to near GND (within RDS(on) × ILOAD). With VS ≈ 0 V, the anode of Dboot sits at VCC, while its cathode connects to VB. Since VB starts near VCC (from prior cycle), the diode is forward-biased, allowing current to flow from VCC through Dboot into Cboot. Cboot charges to approximately VCC – VF(Dboot) (typically 11.3–14.5 V).
Phase 2: High-Side On → Floating Drive Delivery
When LIN goes LOW and HIN goes HIGH, the low-side switch turns off, allowing VS to rise toward VBUS. Dboot becomes reverse-biased, isolating VCC from Cboot. Now, Cboot acts as a local energy source: its negative terminal (connected to VS) floats up with the switching node, while its positive terminal (connected to VB) provides a voltage ~VCC above VS. Thus, when the high-side driver pulls HO to VB, the gate-to-source voltage delivered to the upper MOSFET is VGS(HS) ≈ VB – VS ≈ VCC — precisely what’s needed for full enhancement.
This self-refreshing mechanism works reliably — provided the low-side switch conducts long enough each cycle to fully recharge Cboot. If the high-side duty cycle approaches 100%, Cboot discharges continuously due to high-side driver quiescent current and gate charge consumption, causing VB to sag. Once VB drops below the high-side driver’s undervoltage lockout (UVLO) threshold (typically ~8–10 V), the driver disables the output — risking uncontrolled turn-off or erratic behavior.
Bootstrap Component Selection: Diodes, Capacitors, and Resistors
Component choice directly impacts reliability, efficiency, and maximum achievable frequency/duty cycle.
Bootstrap Diode (Dboot)
Must withstand peak bus voltage (VBUS) plus ringing margin — e.g., for a 400 V bus, select ≥600 V PIV. More critically, it must exhibit low reverse recovery charge (Qrr). During turn-off, reverse recovery current flows *into* Cboot, injecting noise and reducing usable charge. Fast recovery diodes like FR107 (Qrr ≈ 1.5 µC, trr ≈ 500 ns) are standard for 200–600 V buses. For higher frequencies (>100 kHz) or tighter EMI requirements, ultrafast or SiC Schottky diodes (Qrr ≈ 0) are preferred despite higher cost.
Bootstrap Capacitor (Cboot)
Sizing balances droop, ripple, and physical size. Total charge required per cycle is:
Qtotal = Qg(HS) + Iq(HS) × ton(HS)
where Qg(HS) is the high-side MOSFET’s total gate charge, Iq(HS) is the driver’s high-side quiescent current (e.g., 3.5 mA), and ton(HS) is the maximum expected high-side on-time.
Allowable voltage droop (ΔV) is typically 1–2 V. Then:
Cboot ≥ Qtotal / ΔV
A practical rule-of-thumb: start with Cboot = 10–20 × Qg(HS) (in nF if Qg is in nC). For a 100 nC MOSFET, use 1–2 µF. Use low-ESR ceramic (X7R/X5R) for high-frequency response, paralleled with a bulk electrolytic (e.g., 10–22 µF) for low-frequency hold-up.
Gate Resistors
Two resistors per channel serve distinct roles:
- Series gate resistor (RG(on/off)): Controls dV/dt and di/dt, dampens gate-loop resonance (Lg–Ciss), and reduces EMI. Values range from 5 Ω (fast switching, high EMI risk) to 100 Ω (slower, robust). Optimize empirically using oscilloscope measurements of gate waveform and drain overshoot.
- Gate-to-source pull-down resistor (RGSD): Provides a DC discharge path when the driver output is high-impedance (e.g., during startup, fault, or undefined logic state). Prevents Miller-induced false turn-on. Typical values: 1 kΩ to 10 kΩ — i.e., 1000–5000× RG(on/off).
Gate Voltage Clamping
Anti-series Zener diodes (e.g., 12 V + 8 V = 20 V total) clamp VGS to prevent overvoltage stress during transients or negative VS excursions. Their common anode/cathode node must connect *only* to the gate — never shorted to VB, VS, or GND — or the driver’s internal high-side stage may latch up or fail catastrophically.
Driver IC Timing Parameters and Effective Dead Time
Dead time — the intentional blanking interval between high-side turn-off and low-side turn-on (and vice versa) — is the primary hardware defense against shoot-through. But published dead-time specs (e.g., “500–800 ns”) reflect only the driver’s internal logic delay, not the *effective* dead time seen at the power devices.
Consider this asymmetry from a representative driver IC:
| Parameter | Typical Value | Design Implication |
|---|---|---|
| High-side turn-off delay (tOH→OL) | 400 ns | Time from HIN falling edge to HO actually reaching low state |
| Low-side turn-on delay (tIL→OL) | 1000 ns | Time from LIN rising edge to LO actually reaching low state (i.e., pulling VS to GND) |
| Specified dead time (internal) | 500–800 ns | Fixed logic delay inserted between complementary input edges |
| Effective dead time (HS-OFF to LS-ON) | ≥1400 ns | tOH→OL + tIL→OL + internal DT ≈ 400 + 1000 + 500 = 1900 ns |
Thus, the actual minimum non-overlap interval is dominated by the *slowest* transition in the chain — often the low-side turn-on. This extended dead time increases distortion at light loads (due to body-diode conduction) and reduces effective duty cycle resolution. Always verify timing with a differential probe on HO and LO waveforms under real load conditions.
Logic Interlock and Shoot-Through Prevention Architecture
Hardware interlock is a non-negotiable safety feature in modern gate drivers. It overrides software commands to enforce mutually exclusive switching states. A standard truth table for a driver with active-high HIN and active-high LIN inputs is:
| HIN | LIN | HO | LO | State |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | Lower switch ON (safe) |
| 0 | 1 | 0 | 0 | Both OFF (safe) |
| 1 | 0 | 0 | 0 | Both OFF (safe) |
| 1 | 1 | 1 | 0 | Upper switch ON (safe) |
Note that the “forbidden” states — both inputs HIGH or both LOW — result in *both outputs forced LOW*. This guarantees the bridge is never commanded into a shoot-through condition (HS and LS simultaneously ON). Internal weak pull-downs on HIN/LIN ensure default-OFF behavior during MCU reset or signal loss.
Crucially, many drivers use **complementary input logic**: HIN active-high, LIN active-*low*. If your PWM controller outputs standard active-high signals for both channels, connecting them directly violates the interlock assumption and creates guaranteed overlap. Always match controller output polarity to driver input convention — or use external inverters.
Practical Layout and Reliability Best Practices
Even perfect schematics fail without disciplined layout:
- Minimize the bootstrap loop: Route Cboot, Dboot, VB, and VS pins in a tight, low-inductance loop. Any series inductance (Lloop) causes voltage drop L·di/dt during charging, starving Cboot and inducing ringing on VB.
- Decouple VCC locally: Place a 100 nF X7R ceramic capacitor ≤3 mm from the VCC and COM pins. Add a 1–10 µF tantalum or ceramic nearby for bulk storage.
- Separate logic and power grounds: Route VSS (logic ground) returns away from high-current COM paths. Use a single-point star ground or split-plane design to prevent noise injection into logic thresholds.
- Suppress VS transients: A negative spike on VS during HS turn-on (caused by source inductance × di/dt) can forward-bias the driver’s substrate diode, causing false triggering or latch-up. Mitigate with: (1) a dedicated Kelvin source connection from MOSFET source directly to the driver’s VS pin, bypassing the main power trace; (2) a small RC snubber (e.g., 10 Ω + 100 pF) from VS to COM; (3) a fast clamp diode (e.g., BAS16) from VS to COM.
- Layer stacking: Place VB and VS traces on inner layers adjacent to solid ground planes to reduce EMI radiation and improve impedance control.
Finally, treat the driver as one layer in a defense-in-depth protection scheme. Never rely solely on interlock and dead time. Add:
- A hardware over-current comparator monitoring the low-side current sense resistor or bus shunt, feeding a driver disable (DIS) pin.
- Fast desaturation detection on the high-side device (if supported).
- Independent UVLO monitoring on VCC and VB rails.
These features clear faults in <1 µs — orders of magnitude faster than any software-based protection loop.
FAQ
What is the maximum duty cycle achievable with a bootstrap circuit?
Why does my high-side driver stop working after a few seconds at high duty cycle?
Can I use a standard rectifier diode like 1N4007 for Dboot?
My gate waveforms show significant ringing — what’s causing it and how do I fix it?
Is dead time adjustable on most half-bridge drivers?