Power Management IC (PMIC) Design: From Specifications to Silicon

Power Management IC (PMIC) Design: From Specifications to Silicon

Designing a Power Management IC (PMIC) is not merely assembling known blocks — it’s an iterative, specification-driven synthesis where every transistor, resistor, and layout decision traces back to a defined electrical and thermal envelope. This article walks through the complete design flow of a high-efficiency, 5 V-output PMIC as detailed in the foundational tutorial by Liao and Ju — from initial DC-DC topology selection and ripple-constrained filter design, through precision analog sub-blocks like the bandgap reference and over-temperature protection, to silicon-proven layout and simulation practices. Targeted at embedded systems engineers, power IC designers, and hardware architects, this guide grounds each concept in measurable parameters: 90% efficiency at 740 kHz, ±2.3 mV bandgap drift, and 15 °C hysteresis OTP — all realized in a 0.5 µm CMOS process with integrated bipolar devices.

Step 1: Translating System Specs into Topology and Operating Points

Every PMIC starts with a specification sheet — not as marketing copy, but as a binding contract between the IC and the system it powers. For our example chip:

• Input voltage: 2.7–5 V (wide-range USB, battery, or adapter input)
• Output voltage: 5 V ±4% (i.e., 4.8–5.2 V regulation window)
• Output ripple: < ±40 mV peak-to-peak (critical for noise-sensitive analog or RF subsystems)
• Efficiency: ≈90% (dictates thermal budget and battery life)
• Switching frequency: ≤800 kHz (actual operating point ~740 kHz — balances EMI, component size, and MOSFET switching loss)
• Process: 0.5 µm CMOS with on-chip bipolar transistors (enables accurate bandgap and temperature sensing)

Given that the required output (5 V) sits at the upper bound of the input range, a pure buck converter only operates efficiently when V_in > 5 V. Below that — e.g., at 2.7 V — the buck cannot regulate up. Therefore, the full solution must accommodate both regimes: a buck topology dominates above 5 V, while a buck-boost or switched-capacitor (charge-pump) stage handles low-V_in conditions. However, the tutorial focuses on the buck as the core regulated stage — its simplicity, predictability, and dominance in mid-to-high current applications make it the pedagogical and practical anchor.

The buck’s ideal conversion ratio in continuous conduction mode (CCM) is M(D) = D, where D = T_ON/T is the duty cycle. To deliver 5 V from a nominal 3.3 V input, D ≈ 5/3.3 ≈ 1.52 — impossible. So the buck is only viable when V_in ≥ 5.2 V (accounting for ±4% tolerance). In practice, the chip uses hybrid architecture: a primary buck for high-V_in, and a charge-pump boost for low-V_in — leveraging PFM regulation without inductors, ideal for standby or low-current rails.

Step 2: Output Filter Design — Controlling Ripple Through L and C Selection

Ripple isn’t just an AC annoyance — it directly impacts system noise floor, ADC accuracy, and clock jitter. The spec mandates < ±40 mV, which constrains both the inductor and output capacitor. In CCM, the inductor current ripple ΔI_L is:

ΔI_L = (V_in − V_out) × D / (f_sw × L)

For fixed f_sw ≈ 740 kHz and worst-case V_in = 5 V, V_out = 5 V → ΔI_L → 0. But at V_in = 4.5 V, D = 5/4.5 ≈ 0.89, giving:

ΔI_L ≈ (4.5 − 5) × 0.89 / (7.4×10⁵ × L) → magnitude depends on L.

More critically, output voltage ripple has two dominant components:

1. ESR-induced ripple: ΔV_ESR ≈ ΔI_L × ESR_C
2. Capacitor impedance ripple: ΔV_C ≈ ΔI_L / (8 × π² × f_sw² × C)

For ceramic capacitors (low ESR), the second term often dominates. To meet < ±40 mV, designers typically target ΔI_L ≤ 20–30% of I_OUT,MAX and select C such that ΔV_C contributes ≤25 mV. A typical value used in the tutorial is C = 22 µF (X5R, 6.3 V rating), paired with an inductor of ~4.7 µH.

Crucially, the inductor must be sized above the critical inductance L_c to avoid boundary conduction mode (BCM) or discontinuous conduction mode (DCM), which cause variable-frequency operation, higher ripple, and degraded regulation. L_c is given by:

L_c = (V_out × (V_in − V_out)) / (2 × f_sw × V_in × I_OUT,MIN)

If I_OUT,MIN = 1 mA (light-load condition), L_c ≈ 1.8 µH — so L = 4.7 µH provides robust CCM margin.

Step 3: Modulation Strategy — Optimizing Efficiency Across Load Range

A fixed PWM scheme excels at heavy loads but suffers at light loads due to switching losses dominating conduction losses. The solution is hybrid modulation: PWM for high-current operation (>50 mA), and pulse-frequency modulation (PFM) or pulse-skipping modulation (PSM) below that threshold.

• PWM (voltage mode): Compares an error-amplifier output against a fixed-frequency ramp (from a charging capacitor). Simple but requires careful loop compensation.
• PWM (current mode): Uses the sensed switch current as the ramp source. Offers inherent line regulation and easier compensation — but demands slope compensation when D > 0.5 to suppress sub-harmonic oscillation.
• PFM: Holds constant on-time and varies off-time (frequency). Reduces switching loss dramatically at light loads — ideal for IoT or sleep-mode operation.
• PSM: Skips entire switching cycles while maintaining regulated output. Lower complexity than PFM but may increase output ripple during skip intervals.

The tutorial’s 740 kHz design employs current-mode PWM with slope compensation for D > 0.5, transitioning seamlessly to PFM below 10 mA. This achieves the target ~90% efficiency across 1 mA to 1 A loads — verified in HSPICE transient simulations with realistic MOSFET models and PCB parasitics.

Step 4: Bandgap Reference Design — Precision, Stability, and PSRR

The bandgap reference is the PMIC’s “ruler” — its accuracy and stability define regulation tolerance, temperature drift, and power-supply rejection. Our target: 1.19 V ±2.3 mV from −40 °C to 125 °C and 2.5–5 V supply.

This is achieved by combining two complementary temperature-dependent voltages:

• CTAT (Complementary-To-Absolute-Temperature): The base-emitter voltage V_BE of a bipolar transistor decreases with temperature — ≈ −1.5 mV/K near 25 °C.
• PTAT (Proportional-To-Absolute-Temperature): The difference ΔV_BE between two identical transistors biased at current densities differing by factor n is ΔV_BE = (kT/q) × ln(n), yielding ≈ +0.087 mV/K.

The first-order compensated bandgap circuit uses an op-amp to force equality between two nodes, generating a PTAT current through R₁. This current is mirrored and dropped across R₂ to produce a PTAT voltage, then summed with the CTAT V_EB of an output transistor:

V_REF = I_PTAT × R₂ + V_EB

By tuning the R₂/R₁ ratio, the positive PTAT slope cancels the negative CTAT slope at a chosen temperature (e.g., 25 °C), minimizing overall drift.

But precision requires more than theory:

• Start-up circuit: Self-biased current mirrors have two equilibrium points — zero current (undesired latch-up) and nominal current. A dedicated start-up inverter pulls gate voltage high until current flows, then disengages. Without it, the bandgap fails to power up reliably.
• Frequency compensation: The clamp amplifier + output stage forms a 3-stage system. NEST-MILLER compensation (Miller capacitor + resistor between stages 1 and 3) ensures phase margin stays >45° — measured at 52–78° across voltage and temperature corners.
• PSRR enhancement: Conventional cascode loads require ≥2.6 V headroom. The SOOCH (Self-Operating/Offset-Corrected) current-mirror load reduces minimum supply to ≈2 V — enabling operation down to the 2.7 V spec with only 0.6 mV change over 2–6 V.

Measured loop gain: 56–64 dB. Turn-on settling time: <1 µs — tightly aligned with the 1.35 µs period of 740 kHz switching.

Step 5: Over-Temperature Protection (OTP) — Robust Thermal Shutdown

OTP prevents catastrophic die failure from short circuits, overload, or ambient overheating. Its design prioritizes location, accuracy, and robustness.

The sensor is placed physically adjacent to the four large power MOSFETs — the hottest region on-die. Sensing relies on the same bipolar V_EB’s CTAT behavior: as temperature rises, V_EB falls linearly. A precision voltage divider generates a temperature-invariant reference voltage V_REF(ENCE). A comparator (AMP2, PMOS-input for low common-mode voltage ~0.2 V) triggers when V_EB ≤ V_REF(ENCE).

Hysteresis is essential to prevent chatter near the trip point. It’s added via positive feedback: a resistor ladder injects current into the reference node when the comparator output goes high, effectively raising the threshold for turn-off and lowering it for turn-on. The result: clean, stable shutdown at 145 °C, with re-enable only after cooling to 130 °C — a 15 °C hysteresis window.

Corner analysis confirms robustness: MOS threshold variations shift trip point by <1 °C, while resistor ratio mismatches cause ~4–5 °C shifts. For production, laser trimming or steeper V_EB slopes can tighten this further.

Sub-Block Integration and Verification

Beyond bandgap and OTP, the PMIC integrates several support blocks — each co-designed for synergy:

• Oscillator: Sets the ~740 kHz clock. Accuracy directly affects regulation tolerance — a ±3% oscillator variation translates to ±3% output error if uncorrected by feedback.
• Comparator / PWM generator: Compares the feedback voltage (from resistor divider) against V_REF and the current-mode ramp to generate the gate drive signal.
• Driver and protection: High-current gate drivers with slew-rate control minimize EMI; current-limit sensing protects against shorts; UVLO (under-voltage lockout) prevents erratic startup below 2.5 V.

Verification follows a strict hierarchy:

1. Block-level simulation: AC analysis for bandgap stability; DC sweeps for OTP trip point; transient for start-up and load-step response.
2. System-level simulation: Full-switching transient with realistic MOSFET models, PCB inductance, and load steps — validates ripple, efficiency, and regulation.
3. Layout-aware extraction: Post-layout parasitics (capacitance, resistance) are back-annotated and re-simulated. Temperature sensor placement is verified via thermal FEM mapping.

Final sign-off includes corner simulations (FF, SS, FS, SF, TT), Monte Carlo for resistor mismatch, and EM/IR drop analysis on power rails.

PMIC Design Parameter Comparison Table

Frequently Asked Questions (FAQ)