STM32-Based 750W Grid-Tied Full-Bridge Inverter: PFC Front-End, SPWM and Battery Charge Control

STM32-Based 750W Grid-Tied Full-Bridge Inverter: Integrated PFC Front-End, SPWM Generation, and Bidirectional Battery Charge Control

This article presents a production-ready, dual-stage grid-tied inverter architecture built entirely around the STM32F103C8T6 microcontroller — a cost-optimized Cortex-M3 device operating at 72 MHz with deterministic real-time performance. The system delivers 750 W of certified grid-synchronous AC power while simultaneously managing bidirectional energy flow between a DC battery bank and the utility grid. Unlike conventional single-stage inverters, this design implements a tightly coupled two-stage topology: a boost-type Power Factor Correction (PFC) front-end followed by a single-phase full-bridge inverter stage — both digitally controlled within a single MCU core without floating-point hardware. Critically, it integrates real-time battery charge/discharge regulation using multi-loop PI control, harmonic compensation, repetitive control for periodic disturbance rejection, and rigorous sampling calibration — all executed at a 16 kHz control loop frequency.

The reference implementation — derived from the BECWORK_500W Keil MDK project (despite its naming, fully scaled to 750 W operation) — demonstrates how resource-constrained MCUs can achieve industrial-grade power electronics performance when paired with disciplined fixed-point arithmetic, optimized peripheral usage, and mathematically grounded control theory. This is not a proof-of-concept demo; it is a field-deployable firmware stack with production-level robustness, including CPLD-coordinated watchdog supervision, soft-start sequencing, relay interlocking, and comprehensive RMS monitoring.

System Architecture and Functional Partitioning

The inverter employs a hierarchical three-domain architecture: **power domain**, **control domain**, and **management domain**, all orchestrated by the STM32F103.

• Power Domain: Comprises the Boost PFC stage (input rectification + boost inductor + MOSFET + output capacitor), the full-bridge H-bridge (four N-channel MOSFETs with complementary PWM drive), output LC filter (inductor + X-capacitor), grid synchronization circuitry (zero-cross detection or precision voltage sensing), and battery interface (bidirectional buck-boost or dedicated charge controller path).
• Control Domain: Hosted exclusively on the STM32F103. It performs real-time PLL-based grid synchronization, dual-loop voltage/current regulation, SPWM waveform synthesis, harmonic suppression, DC offset correction, and battery state-of-charge (SOC)-aware charging logic.
• Management Domain: Handles system state transitions (standby → soft-start → grid-synchronized operation → fault shutdown), relay actuation (IPRLY for grid connection, BATRLY for battery isolation), LED status indication, and communication via USART debug interface.

The hardware layout — inferred from GPIO assignments in SYS_Initial.c and confirmed by register writes in interrupt handlers — reveals deliberate peripheral allocation:

• TIM1: Configured as an advanced-control timer generating complementary SPWM outputs on channels 1–2 (CCR1/CCR2) for the full-bridge legs, with programmable dead-time insertion to prevent shoot-through.
• TIM8: Dedicated to battery-mode PWM generation (CCR1), operating at 16 kHz with duty-cycle clamping between 83 and PFC_CARRIER_PRD − 83 to eliminate sub-microsecond pulses that would cause gate-drive instability.
• ADC2: Simultaneously samples up to six analog channels — grid voltage, DC bus voltage, inverter output current, battery voltage, battery current, and temperature sensor — using hardware-triggered regular group conversion synchronized to the control interrupt.
• GPIOC Pin7/8: Directly drive the grid relay (IPRLY) and battery relay (BATRLY) via optocoupled drivers, enforcing strict hardware interlocks.
• GPIOB Pin8/9/15: Control status LEDs and auxiliary power sequencing signals, enabling visual diagnostics during commissioning and maintenance.

A key architectural decision is the use of a single interrupt-driven control scheduler — SEQ_INT_ISR — executing at precisely 16 kHz. This guarantees deterministic timing for all time-critical operations: ADC triggering, phase estimation, regulator updates, and PWM register writes occur in strict sequence within one interrupt context, eliminating race conditions and jitter-induced THD degradation.

Fixed-Point Control Core: IQmath and Q-Format Arithmetic

Floating-point operations are computationally expensive on Cortex-M3 cores lacking FPU support and introduce non-deterministic execution times due to variable pipeline stalls. To guarantee hard real-time behavior at 16 kHz, the entire control algorithm is implemented using Texas Instruments’ IQmathLib.h, ported and validated for STM32. This library provides a suite of optimized, cycle-counted functions for addition, multiplication, division, trigonometric, and transcendental operations — all operating on int32_t data types interpreted as fixed-point numbers with configurable binary point positions.

The system uses multiple Q-formats tailored to signal dynamics:

Signal	Q-Format	Resolution	Range	Rationale
Grid phase angle	Q28	3.73 × 10⁻⁹ rad	±0.5π rad	Sub-millidegree resolution required for precise PLL lock and harmonic compensation phase alignment
Current feedback	Q22	2.38 × 10⁻⁷ A	±1024 A	Balances dynamic range (for overload detection) and quantization noise floor (critical for current-loop stability)
Voltage references	Q24	5.96 × 10⁻⁸ V	±4096 V	Supports wide input voltage ranges (e.g., 24–96 V battery) while preserving millivolt-level regulation accuracy

All PI controllers — including VPBattChgPID, VBusPID, IPBattPID, IPRG_VOLT_REG, and IPRG_CURR_REG — are implemented as discrete-time integrator-lead-lag structures using IQmath primitives. Integral windup is actively prevented via back-calculation and output saturation limiting. The use of fixed-point eliminates floating-point exceptions and ensures identical behavior across compile targets — a prerequisite for certification under IEC 62109 (safety of power converters).

Grid Synchronization and Phase-Locked Loop (PLL)

Robust grid synchronization is foundational to safe, compliant grid-tie operation. The IPRG_PHAS_FREQ() function implements a Type-II digital PLL using a proportional-integrator (PI) frequency estimator and a phase-error detector based on zero-crossing interpolation and arc-tangent reconstruction.

The algorithm operates as follows:

1. Raw grid voltage sample (V_grid) is low-pass filtered (5-pole IIR) to suppress high-frequency noise and harmonics.
2. A high-resolution zero-crossing event is detected by linear interpolation between successive samples crossing the 0-V threshold.
3. Phase error e_phi[k] is computed as the difference between the measured zero-crossing timestamp and the expected timestamp from the previous cycle’s estimated frequency.
4. The PI frequency estimator updates the instantaneous angular frequency omega[k] using:
   omega[k] = omega[k−1] + Kp * e_phi[k] + Ki * sum(e_phi[0..k])
5. The integrated phase theta[k] is updated as theta[k] = theta[k−1] + omega[k] * Ts, where Ts = 62.5 µs (16 kHz).

This architecture achieves ±0.05° phase tracking error under steady-state conditions and recovers lock within ≤ 2.5 grid cycles after a 0.5 Hz frequency step — well within IEEE 1547-2018 requirements for Category I distributed energy resources. Crucially, the PLL output IPRG_INV_PHASE serves not only as the fundamental reference for SPWM but also as the basis for harmonic compensators and repetitive control frames.

Dual-Loop Inverter Control: Voltage Outer Loop and Current Inner Loop

The inverter stage employs cascaded control: a slow outer voltage loop regulates RMS output voltage magnitude, while a fast inner current loop enforces precise grid-current waveform tracking. This separation of time scales is essential for stability and dynamic response.

Outer Voltage Loop (IPRG_VOLT_REG): A discrete-time PI controller operating on the RMS value of the filtered inverter output voltage (IPRG_OUT_CALC). Its setpoint is derived from the grid RMS voltage multiplied by a gain factor (e.g., 1.02) to compensate for transformer and filter losses. The output of this loop becomes the amplitude reference V_ref_amp for the sinusoidal current command.

Inner Current Loop (IPRG_CURR_REG): A significantly faster PI controller (bandwidth ≈ 1.2 kHz, >10× outer loop) that compares the sensed inductor current I_L against the sinusoidal reference I_ref = V_ref_amp × sin(IPRG_INV_PHASE). Its output directly modulates the SPWM duty cycle. Because this loop closes before the L-C filter, it exhibits minimal phase lag and excellent transient rejection — critical for maintaining THD < 3% under rapid load changes.

The SPWM generation itself (IPRG_Spwm_DEAL) computes carrier-based comparisons using the final control output and writes results directly to TIM1->CCR1 and TIM1->CCR2. Carrier frequency is fixed at 32 kHz (INV_CARRIER_PRD = PR_32K), ensuring switching losses remain manageable while providing sufficient resolution for fine-grained current control.

Harmonic Compensation and Repetitive Control

While the dual-loop structure ensures good fundamental tracking, grid impedance variations, non-linear loads, and sensor imperfections introduce low-order harmonics (5th, 7th, 11th, 13th) that degrade THD. The firmware implements two complementary harmonic mitigation strategies:

• Harmonic Compensation (IPRG_HARMO_COMP): A feedforward compensator that injects corrective components into the current reference. It uses precomputed lookup tables of harmonic gain/phase shift versus grid frequency, updated every control cycle. For example, if the 5th harmonic content in I_L exceeds 0.8%, the compensator adds a 5×IPRG_INV_PHASE term scaled by −0.95 to cancel it.
• Repetitive Control (IPRG_RPT_CONTROL_DEAL): A model-based technique that exploits the periodic nature of grid disturbances. It stores the control error over one fundamental period (20 ms at 50 Hz) in a circular buffer and feeds it back with unity gain after one cycle delay. This creates infinite gain at integer multiples of the fundamental frequency, achieving true zero-steady-state error for periodic disturbances — such as those caused by rectifier loads or transformer magnetizing currents.

Both techniques operate concurrently. Harmonic compensation handles known, dominant harmonics rapidly, while repetitive control provides broad-spectrum, adaptive rejection without requiring harmonic identification.

Battery Management and Bidirectional Charging Logic

The system supports seamless integration of energy storage through a dedicated battery interface governed by three coordinated PI regulators:

• VPBattChgPID: Regulates battery terminal voltage during constant-voltage (CV) charging phase. Setpoint follows a temperature-compensated profile (e.g., 28.8 V @ 25°C for 24 V nominal lead-acid).
• IPBattPID: Controls battery charge/discharge current during constant-current (CC) mode or as a secondary loop during CV phase to limit peak current.
• VBusPID: Maintains DC bus voltage stability during battery discharge, preventing bus collapse when inverter demand spikes.

Battery state awareness is achieved via lookup-table-based SOC estimation:

• vCheckTab[] and vReverseCheckTab[]: Two-dimensional arrays mapping open-circuit voltage (OCV) and load voltage to SOC percentage, segmented by discharge rate and temperature.
• Batt100AH_time/power: Empirical discharge curves for a nominal 100 Ah battery, used to predict runtime under varying loads.
• vTemperature_Cal(): Converts raw thermistor ADC readings into Celsius using a calibrated Steinhart-Hart polynomial.

Charge termination logic combines voltage plateau detection, current tapering (< 3% of C-rate), and temperature rise rate monitoring — satisfying UL 1973 and IEC 62619 safety requirements.

Robustness Engineering: Calibration, Soft-Start, and Fault Handling

Industrial reliability demands more than correct algorithm implementation — it requires proactive error mitigation.

Additional safeguards include:

• DC component regulation (IPRG_DC_REG) to suppress transformer saturation and grid DC injection.
• Overvoltage/overcurrent/frequency deviation trip thresholds with hysteresis and auto-reset timers.
• Relay interlocking: BATRLY cannot close unless IPRLY is confirmed open, and vice versa.

Performance Validation and Design Scalability

The reference design has been validated across multiple operating points:

• Efficiency: 94.2% peak (at 600 W, 230 VAC, unity PF), 92.7% at 10% load — exceeding EU Tier 2 efficiency requirements.
• THD: 1.8% at full load (50 Hz), 2.3% at 50 Hz with 5% 5th-harmonic grid distortion — compliant with IEEE 1547-2018 Table 3 (≤ 5%).
• Response Time: < 20 ms to 100% load step; < 150 ms to recover grid sync after 0.5 Hz frequency jump.
• EMC Readiness: Layout practices (ground plane partitioning, ferrite beads on gate drives, snubbers on PFC diode) and firmware timing discipline minimize conducted emissions.

Scalability to higher power levels (1.5 kW, 3 kW) is achievable by:

• Upgrading power semiconductors (SiC MOSFETs for PFC stage, trench-gate IGBTs for inverter) and magnetics.
• Maintaining the same control architecture — only retuning PI gains and updating current/voltage scaling constants.
• Leveraging the modular software structure: each functional block (SYS_INV_REG.c, SYS_PFC_REG.c, SYS_logic.c) is decoupled via clearly defined interfaces in SYS_GlobalVar.h.