Bidirectional DC-DC Converter Control for Energy Storage Systems
Bidirectional DC-DC converters form the critical interface between the battery bank and the DC bus in energy storage Power Conversion Systems (PCS). This article examines a production-grade four-phase interleaved bidirectional DC-DC controller implementation on the TMS320F28335 DSP, extracted from a 30 kW battery energy storage PCS. The design features three-stage cascaded PI control, automatic phase shedding for efficiency optimization, and hardware-level CPLD protection interfaces.
1. Interleaved Multiphase Topology Benefits
The converter employs four parallel interleaved phases, with EPWM4 controlling phases 1 and 3, and EPWM5 controlling phases 2 and 4. The interleaving is achieved through phase-shifted PWM carriers:
EPwm4Regs.TBPHS.half.TBPHS = 2288; // Phase shift for phases 1&3
EPwm5Regs.TBPHS.half.TBPHS = 2400; // Phase shift for phases 2&4 (180° offset)The 180° interleaving between the two phase groups produces several advantages:
- Input/output ripple cancellation: The effective ripple frequency at the battery terminals is 4 × 16 kHz = 64 kHz, significantly reducing filter capacitor requirements
- Thermal distribution: Power dissipation is spread across four sets of switching devices and inductors
- Scalability: The modular architecture supports 10–100 kW systems by adjusting the number of active phases
- Fault tolerance: A single phase failure reduces capacity by only 25%, allowing graceful degradation
2. Three-Stage Cascaded Control Architecture
The control system implements a hierarchical cascaded PI structure with three distinct stages, each with its own anti-windup feedback path:
| Stage | Kp | Ki | Kaw | Output Range |
|---|---|---|---|---|
| DC Bus Voltage (outer) | 5147 | 7 | 5 | wBatteryLimitCurrLow … wBatteryLimitCurrHigh |
| Battery Charge Voltage | 5147 | 15 | 12 | -cDCCurrMax … 0 (charge direction) |
| Battery Discharge Voltage | 5147 | 15 | 12 | 0 … cDCCurrResolving (discharge direction) |
| DC Current (inner, per-phase) | 10294 | 264 | 105 | 0% … 90% duty cycle |
The outer voltage loop generates a current reference that feeds four independent per-phase current controllers. Each current controller includes a carrier feedforward term for improved disturbance rejection:
// Carrier feedforward calculation
dwDCModuFedFrwd = (INT32S)8192 - (((INT32S)wDCVolt * wDCPwmCarrFrwd) >> 11);
if (dwDCModuFedFrwd < 0) { dwDCModuFedFrwd = 0; }
// PI output combined with feedforward
dwDCModuPreSat = (((INT64S)dwDCCurrPICtrl * cDCPwmCarr) >> 15) + dwDCModuFedFrwd;This feedforward path predicts the steady-state duty cycle from the voltage transfer ratio, allowing the PI controller to handle only dynamic corrections — dramatically improving transient response during load steps and mode transitions.
3. PI Controller Design with Anti-Windup
Every PI stage in the control chain implements back-calculation anti-windup. When the controller output saturates at the duty cycle limit, the saturation error is fed back through the anti-windup gain (Kaw) to prevent integrator windup:
// Integrator update with anti-windup
dwDCCurrIngCtrl1st = dwDCCurrIngCtrl1st
+ (INT32S)wDCCurrErrFilt * cDCCurrKi
+ (INT32S)dwDCModuSatErr1st * cDCCurrKaw;
// Saturation error for anti-windup
dwDCModuSatErr1st = ((((INT32S)wDCCurrModu - dwDCModuPreSat) * cDCPwmCarrInv) >> 6);The saturation error is computed in the modulation domain and converted back to the current error domain through the inverse PWM carrier gain (cDCPwmCarrInv), ensuring dimensional consistency in the anti-windup path. Without this conversion, the anti-windup gain would need to vary with operating point, making tuning impossible.
4. Mode Transition: Charge to Discharge
Smooth transitions between charge and discharge modes are critical for battery lifetime and grid stability. The controller implements a feedforward-initialized transition sequence:
if (fDCChargeToDisCharge == 1) {
wDCBusVoltErrFiltPrev = 0; // Reset filter state
dwDCBusVoltSatErr = 0; // Clear anti-windup
dwDCBusVoltIngCtrl = dwDCBusVoltIngCtrl + dwDeltaDCCurrTmp; // Feedforward jump
fDCChargeToDisCharge = 0;
}Rather than waiting for the voltage loop integrator to slowly migrate across the zero-current point, the controller directly increments the integrator by a pre-calculated feedforward term (dwDeltaDCCurrTmp) proportional to the inverter’s resolved AC current and the battery-to-bus voltage ratio. This achieves sub-millisecond transition times without voltage overshoot.
5. Phase Shedding for Efficiency Optimization
The controller supports four operating modes selected via the fDCOutEn parameter:
| fDCOutEn | Active Phases | wDCCtrCoeff | Use Case |
|---|---|---|---|
| 0 | None (standby) | 4 | All outputs disabled, integrators reset |
| 1 | Phase 2 only | 8 | Light load (<25% rated) |
| 2 | Phase 4 only | 8 | Light load (<25% rated, alternate) |
| 3 | All 4 phases | 4 | Heavy load (≥25% rated) |
The wDCCtrCoeff parameter adjusts the DC bus voltage error scaling to maintain consistent loop gain regardless of the number of active phases. With two phases active, each phase carries twice the current, so the coefficient doubles from 4 to 8 to maintain the same per-unit control response.
During mode transitions (e.g., from 2-phase to 4-phase), the controller copies the integrator state from the currently running phase to the newly activated phases, ensuring a bumpless transition with zero current discontinuity.
6. Duty Cycle Limits and Hardware Protection
The duty cycle is hard-limited to 90% maximum (0% minimum) to prevent shoot-through from the bootstrap capacitor discharge at high duty cycles and to maintain a minimum off-time for the IGBT:
#define cDCModuLimitHigh 7372 // 90% duty: 7372/8192 ≈ 0.90
#define cDCModuLimitLow 1 // Near 0%, never fully off for bootstrap refresh
if (dwDCModuPreSat > cDCModuLimitHigh) { wDCCurrModu = cDCModuLimitHigh; }
else if (dwDCModuPreSat < cDCModuLimitLow) { wDCCurrModu = cDCModuLimitLow; }Battery voltage limits are enforced at the application level: wBatVolLimtHigh = 9600 (600V, Q4 scaling) and wBatVolLimtLow = 6400 (400V). When either limit is approached, the corresponding voltage loop overrides the bus voltage loop to prevent battery over-charge or deep discharge.
A CPLD hardware shutdown interface (fCPLDShutDCPWM) provides an independent protection path. When asserted, all four current controller integrators are zeroed within 4 interrupt cycles (500 µs at 8 kHz ISR rate), and the current reference is forced to zero.
7. Design Guidelines
- Interleaving phase shift: Verify the phase shift with a logic analyzer at startup. Incorrect TBPHS values cause overlapping on-times that double the input ripple instead of canceling it.
- Anti-windup gain tuning: Set Kaw to approximately Ki/2 for the initial tuning pass, then adjust empirically. Too low and the integrator unwinds slowly after saturation; too high and the anti-windup path can cause low-frequency oscillation.
- Feedforward accuracy: The carrier feedforward term depends on accurate battery voltage sensing. Calibrate the ADC gain and offset before commissioning the feedforward path.
- Phase shedding hysteresis: Add a time delay (e.g., 500 ms) before engaging or disengaging phases to prevent rapid toggling at the boundary load condition.