Case Study: 750W Grid-Tied Full-Bridge Inverter on STM32F103

A production-derived single-phase grid-tied inverter featuring unipolar SPWM at 32 kHz, software PLL grid synchronization, DQ-frame current control, and plug-in repetitive control for harmonic suppression — all on a single 72 MHz Cortex-M3 MCU without an FPU. | Published August 2026 | innovchip.net

1. Project Overview

This 750W single-phase grid-tied full-bridge inverter is built on the STM32F103C8T6 — a 72 MHz Cortex-M3 microcontroller with 64 KB Flash, 20 KB SRAM, and notably no hardware floating-point unit. Despite this constraint, the firmware implements a complete grid-tied inverter stack: unipolar sinusoidal PWM, software phase-locked loop (PLL) for grid synchronization, DQ-rotating-frame current control with cross-axis decoupling, and a multi-channel plug-in repetitive controller for harmonic suppression. The design is clearly derived from an earlier TI C2000 DSP codebase, ported to the ultra-low-cost STM32 platform through careful fixed-point mathematics and resource-aware scheduling.

2. Hardware Topology: Two-Stage Architecture

The inverter employs a two-stage cascaded topology: a front-end boost PFC converter that rectifies and regulates the AC input to a stable 390V DC bus, followed by a single-phase H-bridge inverter that synthesizes the sinusoidal output current using unipolar SPWM. Both stages are controlled by the same STM32F103C8T6, which drives all power switches through two independent timer peripherals.

The H-bridge uses 600V-rated IGBTs in a TO-220 package, operating with unipolar PWM — only two transistors switch at high frequency at any instant while the complementary pair holds steady-state, halving effective switching losses compared to bipolar modulation. The output filter is a single-stage LC low-pass with an inductor in the range of 2–5 mH, sized to attenuate the 32 kHz carrier ripple to below 1% THD at rated load.

3. PWM Strategy: Unipolar SPWM with Bus-Voltage Feedforward

The inverter PWM implements unipolar sinusoidal modulation in SINGLE_MODE. Compared to bipolar SPWM, unipolar modulation doubles the effective switching frequency seen by the output filter (the inductor ripple frequency is 64 kHz at a 32 kHz carrier), significantly reducing filter size while maintaining low switching losses. The modulation index is updated every PWM cycle via the IPRG_Spwm_DEAL function, which computes the duty cycle as:

The sinusoidal reference is drawn from a pre-computed 1024-entry sine table stored in Flash memory, indexed by the phase accumulator. This eliminates runtime trigonometric computation — critical on an MCU without an FPU. The sine values are stored in Q12 fixed-point format (1.0 = 4096), and the duty-cycle registers are loaded in Q10 format after scaling by the modulation index.

4. Control Architecture

4.1 Off-Grid Mode: Cascaded Voltage-Current Loop

In islanded operation, the inverter runs a cascaded dual-loop PI control: the outer voltage loop regulates the AC output voltage amplitude (220V RMS) and generates the inner current reference. The inner current loop tracks this reference with a bandwidth of approximately 1 kHz. Both loops execute at the 32 kHz PWM rate (every 31.25 µs).

4.2 Grid-Tied Mode: DQ-Rotating-Frame Current Control

For grid-connected operation, the control transitions to synchronous-frame (DQ) current control. The grid voltage and inverter current are transformed from the stationary αβ-frame to the rotating DQ-frame using the grid phase angle from the software PLL. The D-axis current (i_d) controls active power, and the Q-axis current (i_q) controls reactive power. Cross-axis decoupling terms compensate for the Lω coupling between the D and Q axes, enabling independent control of active and reactive power.

All DQ-transformation coefficients and PI gains are pre-computed in Q28 fixed-point format for the coordinate transforms and Q10 format for the PI controller, carefully scaled to avoid overflow at maximum modulation index while preserving sub-1% steady-state resolution.

4.3 Software Phase-Locked Loop (PLL)

The PLL locks to the grid voltage zero-crossing using a second-order generalized integrator (SOGI) structure, sampled at 16 kHz. The frequency tracking rate is limited to 0.64 Hz/s to reject transient frequency disturbances. The code includes a zero-crossing jump anticipation feature: if the expected zero-crossing point differs from the actual by more than a configurable threshold, the PLL performs a soft angle correction rather than an abrupt reset, preventing current transients.

4.4 Plug-in Repetitive Control (RC) for Harmonic Suppression

A 4-channel plug-in repetitive controller runs in parallel with the PI current loop to suppress periodic harmonic distortion. Each channel targets a specific harmonic order (3rd, 5th, 7th, and 9th), using a delay-line memory buffer equal to one fundamental period (20 ms for 50 Hz). The RC transfer function includes:

• Damping coefficient (Q < 1): a slight low-pass characteristic to prevent instability at high frequencies
• Dead-zone: disables the RC output when the error is below a configurable threshold, preventing integrator windup from noise
• Output limiting: clamps the RC correction term to ±10% of the PI output, ensuring the RC improves but never destabilizes the current loop

This hybrid PI+RC structure achieves <3% THD on the output current under nonlinear and distorted grid conditions, a significant improvement over standalone PI control.

5. Protection and Fault Handling

6. Software Architecture

The firmware executes from a 16 kHz timer interrupt (TIM4), completing one full control cycle every 62.5 µs. The ISR executes a 9-step sequential chain:

1. Read ADC results (grid voltage, inverter current, DC bus voltage, PFC inductor current)
2. Apply Q10/Q12/Q28 fixed-point scaling to all samples
3. Run PLL phase update and zero-crossing detection
4. Execute DQ-frame transformation (Park/Clarke transforms in Q28)
5. Compute PI current controller output (Q10 → Q12 for PWM mapping)
6. Add repetitive controller correction term
7. Apply cross-axis decoupling and bus-voltage feedforward
8. Update TIM1 compare registers for SPWM duty cycles
9. Check fault status, update state machine, and return

The sine table (1024 × 2 bytes = 2 KB) and all control parameters are stored in Flash. The RAM budget is tight: the repetitive controller’s 4-channel delay buffers alone consume approximately 2.5 KB, leaving about 17 KB for stack, heap, and working variables on the 20 KB SRAM.

7. Key Design Takeaways

1. DSP-to-STM32 Porting Masterclass: The codebase carries clear DNA from a Texas Instruments C2000 DSP design (evident in the naming conventions and control structure), yet it’s been painstakingly ported to a $1.50 Cortex-M3 MCU. The fixed-point mathematics (Q10/Q12/Q28 scale factors), pre-computed sine LUT, and resource-aware ISR scheduling demonstrate how to ship DSP-grade control on a cost-optimized general-purpose MCU.
2. Repetitive Control as a Harmonic Safety Net: Rather than relying on high-bandwidth PI alone, the 4-channel plug-in RC provides targeted harmonic cancellation without destabilizing the main control loop. This is especially valuable for grid-tied inverters operating on weak or distorted grids.
3. Production-Ready Protection: The 9-tier fault hierarchy with hardware cycle-by-cycle limiting, software overcurrent latching, and DC injection detection meets utility-interconnection requirements for distributed generation systems.
4. Single-MCU Integration: Running PFC, inverter PWM, PLL, DQ control, repetitive control, and fault management on a single 72 MHz MCU is an impressive engineering feat. The 16 kHz ISR leaves approximately 40 µs of headroom per cycle for background tasks (communication, EEPROM writes, state machine updates).

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