Case Study: Y068 30kW Bidirectional Storage Inverter
1. Project Overview
The Y068 is a 30kW bidirectional energy-storage Power Conversion System (PCS) designed for commercial and utility-scale battery energy storage applications. The system achieves true bidirectional power flow — charging batteries from the grid (AC→DC) and discharging stored energy back to the grid (DC→AC) — through a coordinated two-stage architecture: a 4-channel interleaved bidirectional Buck/Boost DC/DC converter paired with a T-type three-level IGBT inverter running at 16 kHz. The digital control core is a Texas Instruments TMS320F2833x DSP supplemented by an Altera EPM1270 CPLD for hardware-level PWM interlocking, cycle-by-cycle current limiting, and relay sequencing.
Key System Specifications:
Rated Power: 30 kW | AC Output: 480V 3-phase 60Hz (480V grid per Rule 21) | Battery Voltage Range: 250–950 VDC | Max Battery Current: ±70 A | Switching Frequency: 16 kHz (INV), 20 kHz (DC/DC) | Efficiency Target: >96% (peak) | Communication: CAN 2.0B 500 kbps, RS-485, RS-232, I²C EEPROM
2. Hardware Architecture
2.1 DC/DC Stage — 4-Channel Interleaved Bidirectional Buck/Boost
The DC/DC stage consists of four identical Buck/Boost channels operating in interleaved mode. Under light load (below 50% of rated power or DC current threshold), only channels 1–2 or 3–4 are active. Above the threshold, all four channels engage simultaneously. The PWM signals for channels 1 and 2 are phase-shifted by 180°, as are channels 3 and 4, effectively reducing the DC-link current ripple by a factor of four compared to single-channel operation.
Each channel employs a Fairchild FDS5672 N-channel MOSFET (60V/8.5A) for the buck-side low-voltage gate drive, with STMicroelectronics STTH102A / STTH112A ultrafast recovery diodes (200V/1A) for bootstrap and snubber circuits. The gate drive isolation is implemented using Toshiba TLP5214 smart gate-driver optocouplers, which provide integrated DESAT protection, active Miller clamp, and fault feedback — a critical safety feature for 1200V-class IGBT operation. The current-mode PWM controller ON Semiconductor UC2845BD1 manages the Buck/Boost driver power supply.
| Component | Part Number | Manufacturer | Role |
|---|---|---|---|
| IGBT (all stages) | FGH40T120SMD | Fairchild (onsemi) | 1200V/40A Trench-FS IGBT, TO-247 |
| Gate Driver | TLP5214 | Toshiba | Smart IGBT gate driver with DESAT & Miller clamp |
| Buck MOSFET Driver | FDS5672 | Fairchild | N-ch MOSFET for low-side gate drive |
| PWM Controller | UC2845BD1 | ON Semiconductor | Current-mode PWM for Buck/Boost driver supply |
| Snubber Diode | STTH102A / STTH112A | STMicroelectronics | Ultrafast 200V/1A recovery diode |
| Bootstrap Diode | BAS16HT1 | ON Semiconductor | High-speed switching diode |
| DC/DC Inductor | 4.7 μH / 0.15A (custom) | SCA30K-T02 | 4.7 μH Buck/Boost inductor per channel |
| Current Sense | 0.51Ω shunt | — | Per-channel current feedback |
2.2 Inverter Stage — T-Type Three-Level NPC Topology
The inverter adopts the T-type three-level Neutral-Point-Clamped (NPC) topology using twelve FGH40T120SMD IGBTs (four per phase leg). This topology offers lower conduction losses than conventional two-level inverters at partial load, reduced dv/dt stress on motor/grid-side insulation, and inherently lower output harmonic distortion — all achieved with fewer active devices than a diode-clamped three-level converter. The PWM is generated by the TMS320F2833x’s enhanced PWM modules (ePWM1–6) and routed through the CPLD for dead-time insertion and complementary signal generation.
2.3 Control Board & Peripheral Interfaces
The control board is a shared platform adapted from the manufacturer’s 36kW PV inverter, minimizing hardware redesign. The analog front-end samples 16 channels (three-phase grid voltages, inverter currents, battery voltage/current, DC bus voltages, GFCI current, temperature, and ISO resistance) via the DSP’s 12-bit ADC. Communication interfaces include:
- CAN 2.0B (eCANA) — primary link between DSP and LCD, 500 kbps, 11-bit identifiers with 4-group mailbox filtering
- SCI-A (RS-232) — debug/monitoring interface
- SCI-C (RS-232) — communication with external MCU
- I²C — EEPROM for parameter storage and calibration data
- RS-485 — Modbus for external EMS/SCADA integration
CPLD Role: The Altera EPM1270 CPLD handles hardware-critical real-time functions: complementary PWM generation with dead-time insertion, cycle-by-cycle current limiting via hardware comparator feedback, relay sequencing logic (IGBT + mechanical relay staggered timing), and consolidated fault-signal aggregation to the DSP’s TZ1 trip-zone input.
3. Control Algorithm Design
3.1 DC/DC Control Architecture
The DC/DC stage uses a cascaded dual-loop PI control structure: an inner current loop regulating the inductor current (buck direction: Ibat = Pac / Vbat), and an outer voltage loop regulating the battery port voltage. Since the battery internal EMF (Vbattery_internal) cannot be directly measured, the control model derives it from sampled quantities using power conservation:
Key Control Equations:
Ibus = Pac / Vbus | Ibat = Vbus × Ibus / Vbat_out
The current loop open-loop transfer function: Gi,ol = Kpwm × Kpi(s) / (sL + R), tuned for crossover at ~1 kHz with phase margin > 60°.
A decoupling feedforward term (battery voltage divided by bus voltage) compensates for the nonlinear duty-cycle-to-current relationship inherent in the Buck/Boost topology, linearizing the plant for the PI controller across the full battery voltage range.
3.2 Inverter Control — Vector Control with Bus Voltage Coordination
The inverter side implements synchronous-frame (dq) vector current control with grid-voltage feedforward and cross-axis decoupling. The outer bus-voltage loop generates the active current reference (id,ref), while the reactive current reference (iq,ref) is configurable via multiple modes: fixed power factor, fixed reactive power, PF(P) curve, or Q(U) curve. The SVPWM modulation is implemented for the T-type three-level topology using DSP-optimized space-vector calculations.
The defining characteristic of this PCS is its bus-voltage-coordinated power-flow direction control: during charging, the DC/DC’s bus voltage reference is set slightly lower than the inverter’s reference, causing the DC/DC to sink power from the bus. During discharging, the DC/DC reference is set higher, causing it to source power. This elegant coordination eliminates the need for explicit mode-switching logic and ensures seamless bidirectional transitions.
3.3 Battery Management & State Machine
The firmware implements a full battery charge/discharge state machine that operates autonomously even without a BMS. Charging progresses through three stages: Constant Current / Constant Power → Constant Voltage → Float Charge (for lead-acid batteries). Discharge uses CC/CP mode with automatic transition to undervoltage protection when the battery voltage reaches the configured lower limit. The state machine runs within a 100 μs interrupt service routine, ensuring deterministic response.
The system-level state machine spans six operating modes:
| State | Functions |
|---|---|
| PowerOnMode | Parameter initialization, battery voltage check, phase-sequence detection, ISO/GFCI test, start-up direction decision (DC-side or AC-side) |
| PreCheckMode | Bus capacitor soft-start, relay diagnostics, open-loop inverter voltage check, battery black-start if AC-initiated |
| InvRunMode | Power soft-start ramp, DC/DC 2/4-channel switching, hot-standby management, continuous fault monitoring |
| FaultMode | Recoverable fault handling; auto-restart on fault clearance; configurable DC relay behavior |
| ShutMode | Permanent fault lockout (3 consecutive faults); manual reset or power-cycle required |
| BootloaderMode | Firmware update via CAN bootloader |
3.4 Software Architecture & Module Structure
DSP firmware is structured into 12 modules, compiled under TI Code Composer Studio v3.3 with fixed-point arithmetic (Q15 format: current data /256, other parameters /16 for true values):
- SYSCTR — system state machine and top-level scheduler
- BiDirDCController — bidirectional DC/DC dual-loop PI with decoupling
- InvController — dq vector control, SVPWM, PLL, LVRT/FVRT
- PROTECT — 60+ fault codes with configurable trip thresholds
- PWM / AD / CAP / TIMER — hardware abstraction layers
- Communication stack — I²C, RS-485, SCI (RS-232), CAN
4. California Rule 21 Compliance
A dedicated firmware variant (PCS_30kVA_16kHz_RULE21_20190227) implements full California Rule 21 Phase 1 smart-inverter requirements for the 480V/60Hz grid. The key modifications over the base firmware include:
| Function | Rule 21 Requirement | Implementation |
|---|---|---|
| Voltage Ride-Through (FVRT) | HV2: V≥120%, 0.16s trip; LV3: V<50%, 1.0s ride-through | 4-zone FVRT: continuous operation (88-110%), mandatory operation (50-88%), momentary cessation (others), with reactive current limiting per zone |
| Frequency-Watt (FW) | Active power reduction above 60.1Hz, slope configurable | First-order low-pass filtered frequency measurement: yk = byk-1 + a(xk + xk-1), a=1/(Topen×2/Ts+1), b=1-2a |
| Volt-Watt (VW) | Active power reduction when voltage >106% nominal (newly added) | Same LPF approach as FW; FW and VW follow “first-triggered, first-served” priority arbitration to avoid conflicting commands |
| Volt-VAR (QU) | Default Q(U) curve: Q1=+30% at 92%, Q2=0 at 96.7%, Q3=0 at 103.3%, Q4=-30% at 107% | Dedicated sQUCurveCal function extracted from main reactive-power path; open-loop response time ≤5s per Rule 21 |
| Protection Ranges | Tighter default thresholds: HV1:[110-120%], LV1:[10-88%], HF1:[60.5-65Hz] | Hard-coded defaults in I²C EEPROM block; adjustable ranges limited to prevent out-of-spec settings |
Design Insight — FW/VW Arbitration: Since both Frequency-Watt and Volt-Watt functions control active power (subtracting from the current operating point), a priority conflict arises when both are enabled simultaneously. The firmware resolves this with a simple rule: whichever function triggers first retains control until it exits; the other is blocked from intervening.
5. Communication Protocol
The internal CAN 2.0B protocol uses 11-bit identifiers divided into 4 fields: destination/source address, register group number, and operation type (read/write/reply). Three register groups are defined: Holding Registers (177 parameters: protection thresholds, power settings, battery limits), Remote Control Registers (50 parameters for EMS dispatch: active/reactive power commands, VS/CS mode switching, battery stack status), and Input Registers (80 parameters: real-time telemetry — grid voltages/currents, power, fault codes, status word). Fast-cycle data (faults, status) updates at 20 ms intervals; slow-cycle data (temperatures, energy counters) at 100 ms.
6. Key Technical Highlights
- Production-Ready Bidirectional Topology: The 4-channel interleaved Buck/Boost stage with 180° phase-shifted PWM achieves a 4× effective ripple reduction on the DC bus, enabling smaller filter capacitors and higher power density.
- Seamless Bus-Voltage-Coordinated Power Flow: The elegant “DC/DC reference higher → discharge, lower → charge” coordination scheme eliminates explicit mode-switching logic, enabling sub-cycle bidirectional transitions without current spikes.
- T-Type Three-Level Inverter: Delivers lower switching losses and reduced dv/dt compared to two-level designs. The CPLD offloads real-time dead-time insertion and complementary signal generation from the DSP, freeing CPU cycles for advanced grid-support functions.
- California Rule 21 Phase 1 Compliance: The system demonstrates mature grid-code compliance engineering — FW/VW/QU curves with open-loop response timing, LPF-filtered frequency measurement for FW, first-trigger-priority arbitration between FW and VW, and a 4-zone FVRT implementation with reactive current clamping.
- Complete Battery Management Without BMS: The autonomous 3-stage CC/CV/float charging and CC/CP discharging with UV protection enables standalone operation without a dedicated battery management system, though the CAN protocol reserves full register space for BMS integration.
- Safety-First Hardware Architecture: The TLP5214 smart gate driver provides per-IGBT DESAT detection, the CPLD implements cycle-by-cycle current limiting and cross-conduction prevention, and the consolidated fault tree defines 60+ fault codes with configurable trip thresholds and recovery behavior.
7. FAQ
Q1: What DSP chip is used, and why fixed-point arithmetic?
The system uses the TI TMS320F28335 (TMS320F2833x family), a 32-bit floating-point-capable DSP. Despite its FPU, the codebase is written in fixed-point Q15 format for historical consistency with the manufacturer’s earlier 36kW PV inverter codebase, enabling maximum code reuse. Current data is divided by 256 for true Ampere values; other parameters are divided by 16. The compiler is TI CCS 3.3.
Q2: How is the bidirectional power transition achieved without momentary reverse current?
The transition is fundamentally voltage-coordinated: the DC/DC and inverter controllers each maintain their own bus-voltage PI loops. To switch from charging to discharging, the DC/DC’s bus voltage reference is incremented above the inverter’s reference in firmware. The DC/DC controller then naturally sources current into the bus capacitor, the bus voltage rises, and the inverter’s voltage loop saturates — effectively handing over power-flow control to the DC/DC in a single control cycle without any open-loop transition.
Q3: What are the actual IGBT and gate driver part numbers on the BOM?
The inverter power stage uses Fairchild (now onsemi) FGH40T120SMD — a 1200V/40A Trench Field-Stop IGBT in TO-247 package. The gate driver is the Toshiba TLP5214 smart gate-driver optocoupler, which integrates a DESAT (desaturation detection) circuit, active Miller clamp, undervoltage lockout, and isolated fault feedback into a single 16-pin SO package. This combination provides robust short-circuit protection without external DESAT diodes.
Q4: How does the 2/4-channel DC/DC switching logic work?
A run-time function sBiDirDCModeSwitch, called every 20 ms, monitors the total DC current (Ibat_total) and the current operating power. When power drops below 50% of rated (15 kW) and the current falls below a configurable threshold, channels 3 and 4 are disabled and their PWM outputs gated by the CPLD. When the load rises above the hysteresis threshold, channels 3 and 4 are re-enabled. This minimizes switching losses at light load while maintaining full current capability on demand.
Q5: Is VSG (Virtual Synchronous Generator) mode supported?
Yes. The source tree includes a dedicated PCS_30kVA_16kHz_VSG firmware variant. The CAN protocol reserves register addresses 133–142 for VSG parameters: mode selection (CS/VS), droop control enable, active power-frequency droop coefficient (Kpf), reactive power-voltage droop coefficient (Kqv), and VS voltage/frequency setpoints. VSG mode allows the PCS to emulate synchronous machine inertia, providing frequency stabilization in islanded microgrids.
8. Conclusion
The Y068 30kW bidirectional storage inverter represents a mature, production-grade PCS design that successfully bridges the gap between high-power PV inverter platforms and the emerging energy storage market. Its architecture reuses proven hardware (control board, IGBT power stage, DSP platform) from a 36kW PV product while adding the bidirectional DC/DC stage and comprehensive battery-management firmware. The California Rule 21 compliance implementation — with LPF-filtered FW/VW, 4-zone FVRT, and QU curve support — demonstrates serious grid-code engineering capability. For system integrators and OEMs evaluating PCS platforms, this design offers a well-documented reference with complete source code (CCS 3.3 project, CPLD Verilog, simulation models), detailed design documentation, and a field-proven bill of materials.