Three-Level NPC Inverter SVM Implementation on DSP28335
The three-level Neutral-Point-Clamped (NPC) inverter has become the topology of choice for medium-voltage and high-power energy storage applications, offering lower device voltage stress and reduced output harmonic content compared to two-level topologies. This article dissects a production-grade Space Vector Modulation (SVM) implementation on the Texas Instruments TMS320F28335 DSP, extracted from a 30 kW Power Conversion System (PCS) for battery energy storage. The codebase represents a complete closed-loop grid-tied inverter controller, including software PLL, cascaded PI regulation, DC bus balancing, and LVRT (Low Voltage Ride Through) support.
1. Why NPC? Topology Advantages
The three-level NPC topology uses four switching devices and two clamping diodes per phase leg, producing three voltage levels: +Vdc/2, 0, and -Vdc/2 with respect to the DC-link midpoint. Key benefits include:
- Halved voltage stress: Each device blocks only half the DC bus voltage, enabling the use of 600V/650V IGBTs on an 800–900V bus
- Reduced dv/dt: Step voltage transitions are Vdc/2 rather than Vdc, reducing motor bearing currents and EMI
- Lower THD: Three-level output approximates a sine wave more closely, reducing filter requirements
- Built-in redundancy: Fault-tolerant operation is possible with appropriate modulation strategies
2. Clarke and Park Transforms in Fixed-Point Q14 Format
The DSP28335 is a fixed-point processor without a hardware floating-point unit (the Delfino F28335 variant). All transforms are implemented in Q14 fixed-point format, where the scaling factor 214 = 16384 maps to unity. The macro constants are defined as:
#define cDivide3 5461 // (1/3) * 2^14 = 5461.33 → 5461 Q14
#define cSqrt3 28378 // sqrt(3) * 2^14 = 28377.99 → 28378 Q14
#define cDivideSqrt3 9459 // (1/sqrt(3)) * 2^14 = 9459.49 → 9459 Q14The forward Clarke transform (ABC to αβ) is implemented as:
void sClarke(T_THREE_PHASE_ABC *ptAbc, T_THREE_PHASE_AFBTGM *ptAfBtGm)
{
ptAfBtGm->Af = (INT16S)(((INT32S)((INT32S)ptAbc->a * 2
- ptAbc->b - ptAbc->c) * cDivide3) >> 14);
ptAfBtGm->Bt = (INT16S)(((INT32S)(ptAbc->b - ptAbc->c)
* cDivideSqrt3) >> 14);
}Note the use of 32-bit intermediate accumulation (INT32S) before the right-shift, preventing overflow during multiplication. This is a critical pattern for fixed-point DSP programming: all multiply-accumulate operations must use a double-width accumulator to preserve precision.
The Park transform rotates the stationary αβ frame to the synchronous dq frame using sine and cosine values from a pre-computed 720-point lookup table with 0.5° resolution:
void sPark(T_THREE_PHASE_AFBTGM *ptAfBtGm, T_THREE_PHASE_DQO *ptDQO)
{
ptDQO->d = (INT16S)(((INT32S)ptAfBtGm->Af * wPLLCosTheta
+ (INT32S)ptAfBtGm->Bt * wPLLSinTheta) >> 14);
ptDQO->q = (INT16S)(((INT32S)ptAfBtGm->Af * (-wPLLSinTheta)
+ (INT32S)ptAfBtGm->Bt * wPLLCosTheta) >> 14);
}3. Software Phase-Locked Loop (PLL)
The grid synchronization PLL operates at 8 kHz and tracks both the positive-sequence and negative-sequence components, enabling ride-through during unbalanced grid faults. Key parameters:
| Parameter | Value | Description |
|---|---|---|
| cPLLFreqAngleGain | 42723 (Q20) | Frequency-to-angle integration gain |
| cPLLMaxFreqAdjust | 904 (Q4) | ±9 Hz frequency capture range |
| wPLLKp / wPLLKi | 10507 / 60 | PI controller gains (Q15 format) |
| Sin Table Size | 720 entries | 0.5° angular resolution |
| Update Rate | 8 kHz | ADC interrupt frequency |
The PLL extracts positive-sequence components using an all-pass filter that introduces a 90° phase delay, followed by symmetrical component decomposition. The PI regulator drives the q-axis voltage component to zero, locking the d-axis to the grid voltage vector. Anti-windup is applied to prevent integrator saturation during frequency excursions beyond the ±9 Hz capture range.
4. ePWM Configuration for Three-Level Modulation
Six ePWM modules are deployed on the DSP28335:
- EPWM1–3: Three-level inverter phases A, B, C — center-aligned count up/down mode, TBPRD = 4688 for 16 kHz carrier (150 MHz / (2 × 16000 Hz))
- EPWM4–5: Bidirectional DC-DC converters — 180° interleaved via TBPHS phase shift of 2288 and 2400 counts
- EPWM6: ADC trigger generation at double the inverter carrier frequency (TBPRD = 2344, 32 kHz sampling)
The PWM modules use action qualifier submodules to generate the three-level switching pattern:
EPwm1Regs.AQCTLA.all = 0x0060; // EPWMxA: Set on up-count match, Clear on down-count
EPwm1Regs.AQCTLB.all = 0x0900; // EPWMxB: Clear on up-count match, Set on down-count
EPwm1Regs.CMPCTL.all = 0x0000; // Both CMPA and CMPB load on CTR=ZeroThe trip-zone (TZ) submodule is configured to force outputs low on an external fault signal (TZSEL.bit.OSHT1 = 1), providing hardware-level protection independent of the CPU.
5. Cascaded PI Control Architecture
The control system implements a four-layer cascaded PI structure:
| Control Loop | Kp | Ki | Kaw (Anti-Windup) | Function |
|---|---|---|---|---|
| DC Bus Voltage Outer | 5147 | 12 | 10 | Regulates total DC bus to 780V |
| DC Current Inner | 1086 | 2 | 9 | Shapes battery charge/discharge current profile |
| Inverter Current (d/q) | 9780 | 355 | 149 | Fast inner current regulation at 8 kHz |
| Bus Differential Voltage | 774 | 1 | 1 | NPC midpoint voltage balancing |
The bus differential voltage loop injects a zero-sequence offset into the SVPWM modulation to balance the upper and lower DC-link capacitor voltages. Without this balancer, manufacturing tolerances in capacitor values and asymmetric loading would cause voltage drift and eventual overvoltage on one capacitor.
6. DC Injection Compensation and Modulation Limits
To prevent transformer saturation, DC injection compensation values are applied to the modulation outputs:
#define cInvChkUdComp 16321 // d-axis DC offset compensation
#define cInvChkUqComp 1427 // q-axis DC offset compensationThe modulation index is clamped to ±8191 (half of the 14-bit range), ensuring linear modulation without overmodulation artifacts. SVPWM inherently extends the linear modulation range to approximately 1.15 times that of sinusoidal PWM, but the software limit maintains margin for transient conditions and DC bus balancing.
7. Practical Considerations
- Q-format tracking: Maintain a clear convention throughout the codebase. This project uses Q14 for transforms, Q15 for PI controller gains, Q8 for current references, and Q20 for PLL angle accumulation. Mismatched Q-formats are a common source of debugging headaches in fixed-point DSP projects.
- PLL initialization during faults: The PLL includes an angle-arctangent error computation during LVRT events, re-locking the phase angle within 10 ms of fault clearance using a 50-sample delay window.
- Negative-sequence regulation: Under unbalanced grid conditions, independent positive and negative-sequence current controllers suppress the 100/120 Hz ripple component, preventing DC-link capacitor over-current.